ATPL230A datasheet(55/122 Pages) ATMEL

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ATPL230A [DATASHEET]

Atmel-43053J-ATPL230A-Datasheet_22-Sep-16

9.1.4

Analog Front End control

9.1.4.1 Gain control

This block implements an Automatic Gain Control (AGC) which attenuates the PLC input signal via activating some

outputs of the ATPL230A, so there is no saturation and therefore no distortion in the OFDM signal.

There are 6 outputs of the ATPL230A controlled by this peripheral. AGC0, AGC1, AGC2, AGC3, AGC4 and AGC5.

Please see reference design for further information and recommended external circuitry values.

9.1.4.2 TxRx control

This block modifies the configuration of the external Analog Front End by means of TXRX outputs. There are two

TXRX outputs, one for each TXDRV. These digital outputs are used to modify external filter conditions between trans-

mission and reception. To allow different external circuitry topologies, the polarity of both signals can be inverted by

hardware (see “TXRX Polarity Selector Register” ).

Figure 9-4.

TxRx control block diagram

See reference design for further information about TxRx control.

9.1.5

Carrier Detection

Looking for an easy detection of incoming messages, the PRIME specification defines a carrier detection algorithm

that shall be based on preamble detection and header recognition. ATPL230A implements by hardware a set of

detection techniques to control access to medium, thus improving frame synchronization in reception and decreasing

collision ratio in transmission.

9.2

PHY parameters

A complete description of the PRIME PHY Layer can be found in PRIME specification. Please refer to the PRIME

specification provided by the PRIME Alliance in www.prime-alliance.org

PRIME specifies a complete set of primitives to manage the PHY Layer, and the PHY-SAP (PHY Service Access

Point) from MAC layer. Doc43048 “Atmel PRIME Implementation” integrates all these functions, making them trans-

parent to the final user and simplifying the management.

ATPL230A

Analog

Front - End

Control

Gain

Control

Emiter

Control

TxRx Control

AGC [0:5]

EMIT [0:5]

EMIT [6:11]

TXRX0

TXRX1

External

Analog

Front - End

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