ATPL230A datasheet(37/122 Pages) ATMEL

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ATPL230A [DATASHEET]

Atmel-43053J-ATPL230A-Datasheet_22-Sep-16

8.3.1.11 Peripheral CRC Configuration Register

Name:

VCRC_CONF

Address:

0xFF16

Access:

Read/Write

Reset:

0xC3

This is an 8 bits register used to configure different CRC´s and LFSR´s. This register contains the following control

bits:

• FB_TYPE:

Configures desired circuit feedback type

‘0’: Select circuit feedback type as below.

‘1’: Select circuit feedback type as below.

• MSBF:

Allows to choose byte calculation mode

‘0’: Select the least significant bit (LSB) first to start calculations.

‘1’: Select the most significant bit (MSB) first to start calculations.

• MIRRORED8:

Allows to flip (turn over) the desired CRC size (bytes) in the 32-bit VCRC_CRC register configured by WIDTH1

and WIDTH0 bits.

‘0’: No flipping is performed and the 32-bit VCRC_CRC register will remain unalterable as below.

‘1’: Flip the desired CRC size (bytes) in the 32-bit VCRC_CRC register configured by the control bits WIDTH1

and WIDTH0. For example, if control bits WIDTH1 and WIDTH0 are both set to ‘1’ (CRC size = 4, see link

table), it will flip the four blocks of bytes in the register. In another case when CRC size = 3 (WIDTH1=’1’ and

WIDTH0=’0’), it will flip the first three blocks of bytes (beginning from less significant byte) in the register

ignoring the last byte.

3210

FB_TYPE

MSBF

MIRRORED32

MIRRORED8

CIN

COUT

WIDTH1

WIDTH0

Input

X^5

X^4

X^3

X^2

X^1

X^0

Input

X^5

X^4

X^3

X^2

X^1

X^0

ATPL230A Datasheet(PDF) 37 Page - ATMEL Corporation

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