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ATPL230A Datasheet(PDF) 25 Page - ATMEL Corporation

Part # ATPL230A
Description  ATPL Series Power Line Communications Device
PDF  122 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATPL230A Datasheet(HTML) 25 Page - ATMEL Corporation

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ATPL230A [DATASHEET]
Atmel-43053J-ATPL230A-Datasheet_22-Sep-16
8.1.2
Configurable CRC calculation
PRIME v1.3 version fixes the polynomial to calculate the CRCs. In case that these polynomials were modified, the
CRC peripheral would be used. It is used as a peripheral unit, accessible using the system peripheral registers.
For example, to configure it for PRIME CRC8:
X^8 + X^2 + X + 1
VCRC_POLY = 0x00000007
VCRC_RST = 0x00000000
VCRC_CONF = 0xC0
And to configure it for PRIME CRC32:
x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
VCRC_POLY = 0x04C11DB7
VCRC_RST = 0x00000000
VCRC_CONF = 0xC3
A different set of registers can also be used to set CRC parameters:
X^12 + X^11 + X^3 + X^2 + X + 1
PRIMEPLUS_CRC_POLY = 0x080F
PRIMEPLUS_CRC_RST = 0x0000
PRIMEPLUS_CRC_CONFIG = 0x14
8.2
Advanced Encryption Standard (AES)
One of the additional security functionalities to PRIME v1.3 is the 128-bit AES encryption of data. ATPL230A includes
a hardware implementation of this block, as a peripheral unit.
In transmission, data must be encrypted previously to the use of the PHY_DATA request primitive (see PRIME
specification), in an independent way (note that Beacon PDU, Promotion PDU and Generic MAC header, as well as
several control packets, are not encrypted).
In reception, data passed by the PHY layer is already encrypted and must be decrypted in a subsequent process.
To encrypt a data package with corresponding KEY, the process is as follows:
1. Write the KEY (128 bits long) in AES_KEY register. This step is only needed if a new key is going to be
used (due to a key change or to a reset operation).
2. Write the 128 bits of data to be encrypted in AES_DATA register.
3. Set to ‘1’ the CIPHER control bit in AES_CTL register and then set to ‘1’ the START control bit to start the
operation. This step could be realized as an atomic operation writing 0x03.
4. Wait until the READY bit in AES_CTL register becomes ‘1’ automatically. This bit indicates when the
operation is completed.
5. After that, the encrypted (coded) data package is automatically stored in AES_DATA register.



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