28F032B3 datasheet(21/48 Pages) INTEL

21 / 48 page

SMART 3 ADVANCED BOOT BLOCK

PRELIMINARY

3.5.1

ACTIVE POWER

With CE# at a logic

-low level and RP# at a logic-

high level, the device is in the active mode. Refer to

the DC Characteristic tables for ICC current values.

Active power is the largest contributor to overall

system power consumption. Minimizing the active

current could have a profound effect on system

power consumption, especially for battery

-operated

devices.

3.5.2

AUTOMATIC POWER SAVINGS (APS)

Automatic

Power

Savings

provides

low

-power

operation during read mode. After data is read from

the memory array and the address lines are

quiescent, APS circuitry places the device in a

mode where typical current is comparable to ICCS.,

The flash stays in this static state with outputs valid

until a new location is read.

3.5.3

STANDBY POWER

With CE# at a logic

-high level (VIH) and device in

read mode, the flash memory is in standby mode,

which disables much of the device’s circuitry and

substantially reduces power consumption. Outputs

are placed in a high

-impedance state independent

of the status of the OE# signal. If CE# transitions to

logic

-high

level

during

erase

program

operations, the device will continue to perform the

operation and consume corresponding active power

until the operation is completed.

System engineers should analyze the breakdown of

standby time versus active time and quantify the

respective power consumption in each mode for

their specific application. This will provide a more

accurate measure of application

-specific power and

energy requirements.

3.5.4

DEEP POWER-DOWN MODE

The deep power-down mode is activated when RP#

= VIL (GND

± 0.2 V). During read modes, RP#

going low de-selects the memory and places the

outputs in a high impedance state. Recovery from

deep power-down requires a minimum time of tPHQV

(see

AC Characteristics—Read Operations).

During program or erase modes, RP# transitioning

low will abort the in-progress operation. The

memory contents of the address being programmed

or the block being erased are no longer valid as the

data integrity has been compromised by the abort.

During deep power-down, all internal circuits are

switched to a low power savings mode (RP#

transitioning to VIL or turning off power to the device

clears the status register).

3.6

Power-Up/Down Operation

The device is protected against accidental block

erasure or programming during power transitions.

Power supply sequencing is not required, since the

device is indifferent as to which power supply, VPP

or VCC, powers-up first.

3.6.1

RP# CONNECTED TO SYSTEM

RESET

The use of RP# during system reset is important

with automated program/erase devices since the

system expects to read from the flash memory

when it comes out of reset. If a CPU reset occurs

without

flash

memory

reset,

proper

CPU

initialization will not occur because the flash

memory

may

providing

status

information

instead of array data. Intel recommends connecting

RP# to the system CPU RESET# signal to allow

proper CPU/flash initialization following system

reset.

System designers must guard against spurious

writes when VCC voltages are above VLKO. Since

both WE# and CE# must be low for a command

write, driving either signal to VIH will inhibit writes to

the device. The CUI architecture provides additional

protection since alteration of memory contents can

only occur after successful completion of the two-

step command sequences. The device is also

disabled until RP# is brought to VIH, regardless of

the state of its control inputs. By holding the device

in reset (RP# connected to system PowerGood)

during power-up/down, invalid bus conditions during

power-up can be masked, providing yet another

level of memory protection.

3.6.2

VCC, VPP AND RP# TRANSITIONS

The CUI latches commands as issued by system

software and is not altered by VPP or CE#

transitions or WSM actions. Its default state upon

power-up, after exit from reset mode or after VCC

transitions above VLKO (Lockout voltage), is read

array mode.

28F032B3 Datasheet(PDF) 21 Page - Intel Corporation

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