ISL68134IRAZ datasheet(16/50 Pages) RENESAS

16 / 50 page

ISL68134

FN8817 Rev.1.00

Page 16 of 50

Jun 19, 2017

overall inrush current management strategy or to precisely

control how fast a load IC is turned on. The ISL68134 gives the

system designer several options for precisely and independently

controlling both the delay and ramp time periods. The soft-start

delay period begins when the EN pin is asserted and ends when

the delay time expires.

The soft-start delay and ramp-up/down times can be configured

using the PowerNavigator GUI. The device needs approximately

200µs after enable to initialize before starting to ramp up. When

the soft-start ramp period is set to 0ms, the output ramps up as

quickly as the output load capacitance and loop settings allow. It

is recommended to set the ramps to a non-zero value to prevent

inadvertent fault conditions due to excessive inrush current.

Stored Configuration Selection

As many as eight configurations can be stored and used at any

time using the on-board nonvolatile memory. Configurations are

assigned an identifier number between 0 and 7 at power-up. The

device will load the configuration indicated by the 1% resistor

value detected on the CONFIG pin. Resistor values are used to

indicate use of one of the eight possible configurations. Table 3

shows the resistor value corresponding to each configuration

identifier.

Only the most recent configuration with a given number can be

loaded. The device supports a total of eight stored operations. As

an example, a configuration with the identifier 0 could be saved

eight times or configurations with all eight identifiers could be

stored one time each for a total of eight save operations.

PowerNavigator provides a simple interface to save and load

configurations.

Fault Monitoring and Protection

The ISL68134 actively monitors temperature, input voltage, output

voltage, and output current to detect and report fault conditions.

Fault monitors trigger configurable protective measures to prevent

damage to a load. The power-good indicators, PG0/PG1, are

provided for linking to external system monitors.

A high level of flexibility is provided in the ISL68134 fault logic.

Faults can be enabled or disabled individually. Each fault type can

also be configured to either latch off or retry indefinitely.

Power-Good Signals

The PG0/PG1 pins are open-drain, power-good outputs that

indicate completion of the soft-start sequence and output

voltage of the associated rail within the expected regulation

range.

The PG pins can be associated or disassociated with a number of

the available fault types. This allows a system design to be tailored

for almost any condition. In addition, these power-good indicators

will be pulled low when a fault (OCP or OVP) condition or UV

condition is detected on the associated rail.

Output Voltage Protection

Output voltage is measured at the load sensing points

differentially for regulation and the same measurement is used

for OVP and UVP. The fault thresholds are set using PMBus

commands. Figure 17 shows a simplified OVP/UVP block

diagram. The output voltage comparisons are done in the digital

domain.

The device responds to an output overvoltage condition by

disabling the output, declaring a fault, setting the SALRT pin,

setting the PG pin and then pulsing the LFET until the output

voltage has dropped below the threshold. Similarly, the device

responds to an output undervoltage condition by disabling the

output, declaring a fault, setting the SALRT pin, and setting the

PG pin. The output will not restart until the EN pin is cycled

(unless the device is configured to retry).

In addition, the ISL68134 features open pin sensing protection to

detect an open of the output voltage sensing circuit. When this

condition is detected, controller operation is suspended.

Output Current Protection

The ISL68134 offers a comprehensive overcurrent protection

scheme. Each phase is protected from both excessive peak

current and sustained current. In addition, the system is

protected from sustained total output overcurrent.

Figure 18 on page 17 depicts a block diagram of the system total

output current protection scheme. In this scheme, the phase

currents are summed to form ISUM. ISUM is then fed to dual

response paths allowing the user to program separate LPF,

threshold, and response time. One path is intended to allow

response more quickly than the other path. With this system, the

user can allow high peak total current for a short time and a

lower level of current for a sustained time. Note that neither of

TABLE 3. RESISTOR VALUES TO CONFIGURATION MAPPING

R CONFIG

(Ω)

CONFIG

6800

1800

2200

2700

3300

3900

4700

5600

FIGURE 17. OVP, UVP COMPARATORS

RGNDx

VSENx

ADC

ISL68134

DIGITAL OV

COMPARATOR

THRESHOLD

DIGITAL UV

COMPARATOR

THRESHOLD

SoC

ISL68134IRAZ Datasheet(PDF) 16 Page - Renesas Technology Corp

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