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ISL6334DIRZ Datasheet(PDF) 17 Page - Renesas Technology Corp

Part # ISL6334DIRZ
Description  VR11.1, 4-Phase PWM Controller with Phase Dropping, Droop Disabled and LoadCurrent Monitoring Features
PDF  28 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL6334DIRZ Datasheet(HTML) 17 Page - Renesas Technology Corp

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ISL6334D
FN6802 Rev 4.00
Page 17 of 28
Apr 29, 2016
Output-Voltage Offset Programming
The ISL6334D allows the designer to accurately adjust the offset
voltage. When a resistor, ROFS, is connected between OFS to
VCC, the voltage across it is regulated to 1.6V. This causes a
proportional current (IOFS) to flow into OFS. If ROFS is connected
to ground, the voltage across it is regulated to 0.4V, and IOFS
flows out of OFS. A resistor between DAC and REF, RREF, is
selected so that the product (IOFS x ROFS) is equal to the desired
offset voltage. These functions are shown in Figure 10.
Once the desired output offset voltage has been determined, use
Equations 8 and 9 to calculate ROFS:
For Positive Offset (connect ROFS to VCC):
For Negative Offset (connect ROFS to GND):
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-voltage
regulator to do this by making changes to the VID inputs during
regulator operation. The power management solution is required
to monitor the DAC inputs and respond to on-the-fly VID changes
in a controlled manner. Supervising the safe output voltage
transition within the DAC range of the processor without
discontinuity or disruption is a necessary function of the
core-voltage regulator.
In order to ensure the smooth transition of output voltage during
VID change, a VID step change smoothing network, composed of
RREF and CREF, as shown in Figure 10, can be used. The selection
of RREF is based on the desired offset voltage, as detailed in
“Output-Voltage Offset Programming” on page 17. The selection
of CREF is based on the time duration for 1-bit VID change and
the allowable delay time.
1010
0
000
0.61250
1
0
1
0
0
0
0
1
0.60625
1
0
1
0
0
0
1
0
0.60000
1010
0
011
0.59375
1010
0
100
0.58750
1010
0
101
0.58125
1010
0
110
0.57500
1010
0
111
0.56875
1
0
1
0
1
0
0
0
0.56250
1
0
1
0
1
0
0
1
0.55625
1
0
1
0
1
0
1
0
0.55000
1010
1
011
0.54375
1010
1
100
0.53750
1010
1
101
0.53125
1
0
1
0
1
1
1
0
0.52500
1010
1
111
0.51875
1011
0
000
0.51250
1
0
1
1
0
0
0
1
0.50625
1
0
1
1
0
0
1
0
0.50000
1111
1
110
OFF
1111
1
111
OFF
TABLE 3. VR11 VID 8-BIT (Continued)
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VOLTAGE
DYNAMIC
VID D/A
E/A
VCC
DAC
FB
REF
OFS
VCC
GND
+
-
+
-
0.4V
1.6V
OR
GND
ROFS
RREF
ISL6334D
FIGURE 10. OUTPUT VOLTAGE OFFSET PROGRAMMING
CREF
ROFS
1.6 RREF
VOFFSET
------------------------------
=
(EQ. 8)
ROFS
0.4 RREF
VOFFSET
------------------------------
=
(EQ. 9)



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