ISL6334DIRZ datasheet(25/28 Pages) RENESAS

25 / 28 page

ISL6334D

FN6802 Rev 4.00

Page 25 of 28

Apr 29, 2016

response, the output voltage initially deviates by an amount, as

shown in Equation 30:

The filter capacitor must have sufficiently low ESL and ESR so

that

V < VMAX.

Most capacitor solutions rely on a mixture of high-frequency

capacitors with relatively low capacitance in combination with

bulk capacitors having high capacitance but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the bulk

capacitors allows them to supply the increased current with less

output voltage deviation.

The ESR of the bulk capacitors also creates the majority of the

output-voltage ripple. As the bulk capacitors sink and source the

inductor AC ripple current (see “Interleaving” on page 11 and

Equation 2), a voltage develops across the bulk-capacitor ESR

equal to IC,(P-P)(ESR). Thus, once the output capacitors are

selected, the maximum allowable ripple voltage, VP-P(MAX),

determines the lower limit on the inductance, as shown in

Equation 31.

Since the capacitors are supplying a decreasing portion of the

load current while the regulator recovers from the transient, the

capacitor voltage becomes slightly depleted. The output

inductors must be capable of assuming the entire load current

before the output voltage decreases more than

VMAX. This

places an upper limit on inductance.

Equation 32 gives the upper limit on L for the cases when the

trailing edge of the current transient causes a greater

output-voltage deviation than the leading edge. Equation 33

addresses the leading edge. Normally, the trailing edge dictates

the selection of L because duty cycles are usually less than 50%.

Nevertheless, both inequalities should be evaluated, and L

should be selected based on the lower of the two results. In each

equation, L is the per-channel inductance, C is the total output

capacitance, and N is the number of active channels.

Switching Frequency Selection

There are a number of variables to consider when choosing the

switching frequency, as there are considerable effects on the

upper MOSFET loss calculation. These effects are outlined in

“MOSFETs” on page 23, and they establish the upper limit for the

switching frequency. The lower limit is established by the

requirement for fast transient response and small output-voltage

ripple as outlined in “Output Filter Design” on page 24. Choose

the lowest switching frequency that allows the regulator to meet

the transient-response requirements.

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper MOSFETs.

Their RMS current capacity must be sufficient to handle the AC

component of the current drawn by the upper MOSFETs, which is

related to duty cycle and the number of active phases.

VESL

 di

-----

ESR

 I



(EQ. 30)

ESR



VIN NVOUT

–



 V

OUT

fSVINVP-P MAX



------------------------------------------------------------



(EQ. 31)

2NCVO

I

2

---------------------

V

MAX

I ESR



–



(EQ. 32)

1.25

NC

I

2

--------------------------

V

MAX

IESR



–

VIN VO

–







(EQ. 33)

0.3

0.1

0.2

FIGURE 21. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs

DUTY CYCLE FOR 2-PHASE CONVERTER

00.4

1.0

0.2

0.6

0.8

DUTY CYCLE (VO/VIN)

IL(P-P) = 0

IL(P-P) = 0.5 IO

IL(P-P) = 0.75 IO

DUTY CYCLE (VO/VIN)

FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs

DUTY CYCLE FOR 3-PHASE CONVERTER

00.4

1.0

0.2

0.6

0.8

0.3

0.1

0.2

IL(P-P) = 0

IL(P-P) = 0.25 IO

IL(P-P) = 0.5 IO

IL(P-P) = 0.75 IO

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