ISL6334D

FN6802 Rev 4.00

Page 24 of 28

Apr 29, 2016

power stage, i.e. the temperature effect on the current sense

resistance of the current sense element at room temperature.

When the integrated temperature compensation function is

disabled by pulling the TCOMP pin to GND, the sensed current will

be dependent on the operational temperature of the power

stage, since the DC resistance of the current sense element may

Equation 27 should be the maximum DC resistance of the

current sense element at the all operational temperature.

In certain circumstances, it may be necessary to adjust the value

of one or more ISEN resistors. When the components of one or

more channels are inhibited from effectively dissipating their

heat so that the affected channels run hotter than desired,

the desired decrease in temperature rise in order to cause

proportionally less current to flow in the hotter phase, as shown

in Equation 28:

In Equation 28, make sure that

rise above the ambient temperature, and

temperature rise above the ambient temperature. While a single

adjustment according to Equation 28 is usually sufficient, it may

achieve optimal thermal balance between all channels.

Compensation

The ISL6334D converter can be accurately modeled as a

voltage-mode regulator with two poles at the L-C resonant

frequency and a zero at the ESR frequency. A type III controller,

as shown in Figure 20, provides the necessary compensation.

compensated system. Choose a frequency high enough to assure

adequate transient performance but not higher than 1/3 of the

switching frequency. The type III compensator has an extra

rejection or to assure adequate attenuation at the error-amplifier

high-order pole and zero frequencies. A good general rule is to

shift below the system bandwidth.

In the solutions to the compensation equations, there is a single

degree of freedom. For the solutions presented in Equation 29,

compensation components are then selected.

In Equation 29, L is the per-channel filter inductance divided by

the number of active channels; C is the sum total of all output

capacitors; ESR is the equivalent-series resistance of the bulk

signal amplitude, typically 1.5V.

Output Filter Design

The output inductors and the output capacitor bank together to form

a low-pass filter responsible for smoothing the pulsating voltage at

the phase nodes. The output filter also must provide the transient

energy until the regulator can respond. Because it has a low

bandwidth compared to the switching frequency, the output filter

necessarily limits the system transient response. The output

capacitor must supply or sink load current while the current in the

output inductors increases or decreases to meet the demand.

In high-speed converters, the output capacitor bank is usually the

most costly (and often the largest) part of the circuit. Output filter

design begins with minimizing the cost of this part of the circuit.

The critical load parameters in choosing the output capacitors are

the maximum size of the load step,

I; the load-current slew rate,

di/dt; and the maximum allowable output-voltage deviation under

transient loading,

to their capacitance, ESR, and ESL (equivalent series inductance).

At the beginning of the load transient, the output capacitors supply

all of the transient current. The output voltage will initially deviate by

an amount approximated by the voltage drop across the ESL. As the

load current increases, the voltage drop across the ESR increases

linearly until the load current reaches its final value. The capacitors

selected must have sufficiently low ESL and ESR so that the total

output-voltage deviation is less than the allowable maximum.

Neglecting the contribution of inductor current and regulator

T

2

T

1

----------

=

(EQ. 28)

FIGURE 20. COMPENSATION CIRCUIT

ISL6333

COMP

FB

VSEN



1

–









2





LC



 R









-----------------------------------------------------------------------------------------------------

=







2



  



1

–









-----------------------------------------------------------------------------------------

=

CESR



LC



C ESR



–

--------------------------------------------



=

LC



C ESR



–

--------------------------------------------

=

2





LC



 R









-----------------------------------------------------------------------------------------------------

=

(EQ. 29)