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FS98O02B-PCE Datasheet(PDF) 29 Page - Fortune Semiconductor Corp.

Part # FS98O02B-PCE
Description  8-bit MCU with 2k program EPROM, 128-byte RAM
PDF  50 Pages
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Manufacturer  FORTUNE [Fortune Semiconductor Corp.]
Direct Link  https://www.ic-fortune.com/eng/index.asp
Logo FORTUNE - Fortune Semiconductor Corp.

FS98O02B-PCE Datasheet(HTML) 29 Page - Fortune Semiconductor Corp.

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FS98O02
Rev.1.5
29/50
16.3 ADC Control Register
There are some ADC control related registers in FS98O02. There will be some more detail descriptions
about using the ADC control register to get the proper ADC operation in users’ applications.
Table 16-1: ADC Control Related Registers
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
WDT Reset State
06h
INTF
ADIF
---0 --00
---0 --00
07h
INTE
GIE
ADIE
0--0 --00
0--0 --00
10h
ADOH
ADO [23:16]
0000 0000
0000 0000
11h
ADOM
ADO [15:8]
0000 0000
0000 0000
12h
ADOL
ADO [7:0]
0000 0000
0000 0000
13h
ADCON
ADRST
ADM [2:0]
---- 0000
---- 0000
2Fh
NETG
ADG [1:0]
ADEN
AZ
---- 0000
---- 0000
IN+
IN-
VRH
VRL
{ADOH, ADOM, ADOL}
VIH
VIL
MUX
AZ
Modulator
Digital
Comb
Filter
ADG [1:0]
ADRST
ADEN
Figure 16-1: the Block Diagram of ADC
The ADC contains a ΔΣ modulator and a digital comb filter. When ADEN = 1, the ΔΣ modulator (ADC) will
be enabled. When ADEN = 0, the ΔΣ modulator (ADC) will be disabled. When ADRST = 1, the digital comb filter
will be enabled. When ADRST = 0, the digital comb filter will be reset.
16.3.1
ADC Output Rate and Settling Time
The ΔΣ ADC is generally an over-sampling ADC. The ADC’s each digital output code is the result of
sampling the input signal N times and processed by DSP. The ADC’s sampling frequency is decided by ADCF.
ADM decides when to send out a 16-bit digital code after sampling N times, and raises an interrupt signal
every time the ADC produces a digital output code. In fact, the ADC’s each digital output code is the result from
the previous 2*N times sampling results. If any of the ADC’s input, reference voltage, ADG or AZ is switched,
the first two output codes are normally not stable, and the third output code and later codes are stable for
calculation.
The ADC’s output rate is selected by ADM [2:0] as described in Table 16-2.
Table 16-2: ADC Output Rate
ADM [2:0]
ADC Output Rate
000
ADCF/125 (~320Hz for 1MHz MCK or ~1.28kHz for 4MHz MCK)
001
ADCF/250 (~160Hz for 1MHz MCK or ~640Hz for 4MHz MCK)



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