FS98O02B-PCE datasheet(24/50 Pages) FORTUNE

24 / 50 page

FS98O02

Rev.1.5

24/50

13. Clock System

The clock system offers several clocks to some important blocks in FS98O02, such as CPU clock, ADC

sample frequency, beeper clock, voltage doubler operating frequency, etc. Only with the clock signals from the

clock system, the FS98O02 can work normally.

Table 13-1: Clock System Related Registers

Address

Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

Bit 2

Bit 1

Bit 0

Reset State

WDT Reset State

09h

PCK

S_CHCK[1:0]

S_BEEP EN_OSC4M ---- 0000

---- 0000

1MHz / 4MHz

Internal Oscillator Circuit

MCK

EN_OSC4M

Figure 13-1: Internal Clock for CPU and Other Blocks

13.1 Oscillator State

MCK is the heart of the clock system. Almost all clock signals are derived from the MCK. If we stop MCK,

many clock signals will be stopped. We may use “sleep” instruction to disable MCK as described in Table 13-2.

When EN_OSC4M = 0（default）,the MCK is about 1MHz. When EN_OSC4M = 1, the MCK is about 4MHz.

Table 13-2: How to Use MCK

Sleep

MCK

Disable

Enable

13.2 CPU Instruction Cycle

The CPU in FS98O02 has only one mode of instruction cycle. That is MCK/4 (~4us for 1MHz MCK or ~1us

for 4MHz MCK).

13.3 ADC Sample Frequency

ADC sample frequency decides the sampling rate of the input signal. The sampling rate of ADC in

FS98O02 is fixed to MCK/25.

Table 13-3: ADC Sampling Frequency

ADC Sample Frequency (ADCF)

MCK/25 (~40kHz for 1MHz MCK or ~160kHz for 4MHz MCK)

13.4 Beeper Clock

We may set beeper clock by select the proper value of S_BEEP as in Table 13-4.

Table 13-4: Setting Beeper Clock

FS98O02B-PCE Datasheet(PDF) 24 Page - Fortune Semiconductor Corp.

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