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FS98O02B-PCE Datasheet(PDF) 38 Page - Fortune Semiconductor Corp. |
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FS98O02B-PCE Datasheet(HTML) 38 Page - Fortune Semiconductor Corp. |
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38 / 50 page  FS98O02 Rev.1.5 38/50 use the same method to light on the dots on the cross position of SEG0 to SEG7 and COM4 to COM1. 19. CPU Reset The FS98O02 CPU has three reset signals and they are external reset (RST_), low voltage reset (LVR), and watchdog time out reset. When resetting, the CPU’s program counter (PC) is reset to 0. After reset finished, the CPU starts working. Table 19-1 shows the CPU’s internal registers status after reset. Table 19-1: the CPU’s Internal Registers Status after Reset Address Name Reset State WDT Reset State 00h IND0 uuuu uuuu uuuu uuuu 02h FSR0 uuuu uuuu uuuu uuuu 04h STATUS ---0 0uuu ---u 1uuu 05h WORK uuuu uuuu uuuu uuuu 06h INTF ---0 –00 ---0 --00 07h INTE 0--0 –00 0--0 --00 09h PCK ---- 0000 ---- 0000 0Ah EADRH uuuu uuuu uuuu uuuu 0Bh EADRL uuuu uuuu uuuu uuuu 0Ch EDAH uuuu uuuu uuuu uuuu 0Dh TMOUT 0000 0000 0000 0000 0Eh TMCON 1000 0000 1u00 0000 0Fh TMMOD 0000 0000 0000 0000 10h ADOH 0000 0000 0000 0000 11h ADOM 0000 0000 0000 0000 12h ADOL 0000 0000 0000 0000 13h ADCON ---- 0000 ---- 0000 1Fh SVD ---- ---1 ---- ---1 20h PT1 uuuu uuuu uuuu uuuu 21h PT1EN 0000 ---- 0000 ---- 22h PT1PU 0000 0000 0000 0000 23h PT1MR 00-- --00 00-- --00 24h PT2 ---- uuuu ---- uuuu 25h PT2EN ---- 0000 ---- 0000 26h PT2PU ---- 0000 ---- 0000 2Ah NETB -000 00-0 -000 00-0 2Ch NETD u000 uu00 u000 uu00 2Eh NETF 0000 0100 0000 0100 2Fh NETG ---- 0000 ---- 0000 33h NETK 0000 0000 0000 0000 40h LCD1 uuuu uuuu uuuu uuuu 41h LCD2 uuuu uuuu uuuu uuuu 42h LCD3 uuuu uuuu uuuu uuuu 43h LCD4 uuuu uuuu uuuu uuuu 44h LCD5 uuuu uuuu uuuu uuuu 45h LCD6 uuuu uuuu uuuu uuuu Note 1: “u” means unknown or unchanged. “-“ means unimplemented, read as “0”. Note 2: The “Reset State” indicates the registers state after external reset and low voltage reset. Note 3: The “WDT Reset State” indicates the registers state after watchdog time out reset. 19.1 External Reset The CPU has a “VPP/RST/TST” pin for external reset usage. When “VPP/RST/TST” is in logic “low” state |
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