ZSSC3018BA2C datasheet(31/51 Pages) RENESAS

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ZSSC3018 Datasheet

September 8, 2020

3.6.2 Memory Contents

Table 3.5 MTP Memory Content Assignments

MTP Address

Word / Bit

Range

Default

Setting

Description

Notes / Explanations

00HEX

15:0

0000HEX

Cust_ID0

Customer ID byte 0 (combines with memory word 01HEX to

form customer ID)

01HEX

15:0

0000HEX

Cust_ID1

Customer ID byte 1 (combines with memory word 00HEX to

form customer ID)

Interface Configuration

02HEX

6:0

000 0000BIN

Slave_Addr

I²C slave address; valid range: 00HEX to 7FHEX (default:

00HEX). Note: address codes 04HEX to 07HEX are reserved for

entering the I2C High Speed Mode

8:7

00BIN

INT_setup

Interrupt configuration, EOC pin functionality:

00 End-of-conversion signal

01 0-1 transition if threshold1 (TRSH1) is exceeded

and 1-0 transition if threshold1 is underrun again

10 0-1 transition if threshold1 is underrun and 1-0

transition if threshold1 is exceeded again

11 EOC is determined by threshold settings (see

section 3.3):

If (TRSH1 > TRSH2) then EOC/INT (interrupt

level) = 0 if (TRSH1 > MEAS ≥ TRSH2) where

MEAS is the conditioned measurement result.

Otherwise EOC/INT=1.

If (TRSH1 ≤ TRSH2) then EOC/INT = 1 if (TRSH1

≤ MEAS < TRSH2). Otherwise EOC/INT = 0.

0BIN

SS_polarity

Determines the polarity of the Slave Select pin (SS) for SPI

operation:

0  Slave Select is active LOW (SPI and ZSSC3018

are active if SS==0)

1  Slave Select is active HIGH (SPI and ZSSC3018

are active if SS==1)

11:10

00BIN

CKP_CKE

Clock polarity and clock-edge select—determines polarity

and phase of SPI interface clock with the following modes:

00  SCLK is low in idle state, data latch with rising

edge and data output with falling edge

01  SCLK is low in idle state, data latch with falling

edge and data output with rising edge

10  SCLK is high in idle state, data latch with falling

edge and data output with rising edge

11  SCLK is high in idle state, data latch with rising

edge and data output with falling edge

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