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ZSSC3018BA2C Datasheet(PDF) 38 Page - Renesas Technology Corp |
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ZSSC3018BA2C Datasheet(HTML) 38 Page - Renesas Technology Corp |
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38 / 51 page  ZSSC3018 Datasheet © 2020 Renesas Electronics Corporation 38 September 8, 2020 MTP Address Word / Bit Range Default Setting Description Notes / Explanations 37HEX 15:0 0000HEX Not assigned (e.g., can be used for Cust_IDx customer identification number) 38HEX 15:0 0000HEX Not assigned (e.g., can be used for Cust_IDx customer identification number) 39HEX 15:0 - Checksum Checksum generated for whole memory through a linear feedback shift register (LFSR); signature is checked with power-up to ensure memory content integrity The memory integrity checksum (referred to as CRC) is generated through a linear feedback shift register with the polynomial: g(x) = x16 + x15 + x2 + 1 with the initialization value: FFFFHEX. If the CRC is valid, then the “Memory Error” status bit is set to 0. |
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