ZSSC3018 Datasheet

© 2020 Renesas Electronics Corporation

11

September 8, 2020

Figure 2.2 ZSSC3018 Functional Block Diagram, Voltage-Source-Sensor

INP

INN

VSSB

AGND / CM

Generator

Bias Current

Generator

Power-ON

Reset

Temperature

Reference

Sensor

DSP Core

(Calculations,

Communication)

MTP

System

Control Unit

Pre-Amplifier

EOC

VDD

Oscillator

Clock Generator

SPI

I²C

SCLK/SCL

MISO

MOSI/SDA

SS

VSS

Power Ctr.

Vreg int

A

18 Bit

VDDB

ZSSC3018

RES

D

PGA

ADC

18 bit

MUX

Voltage Regulator

Analog

Digital

Interface

Functionality Support

The amplifier consists of two stages with programmable gain values.

The ZSSC3018 employs a programmable analog-to-digital converter (ADC) optimized for conversion speed and noise suppression. The

programmable resolution from 12 to 18 bits provides flexibility for adapting the conversion characteristics. To improve power supply noise

is a bridge-type element.

The remaining IC-internal offset and the sensor element offset, i.e., the overall system offset for the amplifier and ADC, can be canceled by

means of an offset and auto-zero measurement, respectively.

correction coefficients are stored in the MTP memory.