ADF4401ABCEZ datasheet(34/39 Pages) AD

34 / 39 page

ADF4401A

Data Sheet

Rev. 0 | Page 34 of 39

Address: 0x36, Default: 0x30, Name: REG0036

Res erved.

[7:0] ICP_ADJUST_OFFSET (R/W)

Table 40. Bit Descriptions for REG0036

Bit(s)

Bit Name

Description

Default

Access

[7:0]

ICP_ADJUST_OFFSET

Reserved.

0x30

R/W

Address: 0x37, Default: 0x00, Name: REG0037

Selects Band in Core when Tes t Mode

is Enabled.

[7:0] SI_BAND_SEL (R/W)

Table 41. Bit Descriptions for REG0037

Bit(s)

Bit Name

Description

Default

Access

[7:0]

SI_BAND_SEL

Selects Band in Core when Test Mode is Enabled.

0x0

R/W

Address: 0x38, Default: 0x00, Name: REG0038

Selects Core when Tes t Mode is

Enabled.

Sets VCO Bias when Tes t Mode is

Enabled.

[7:4] SI_VCO_SEL (R/W)

[3:0] SI_VCO_BIAS_CODE (R/W)

Table 42. Bit Descriptions for REG0038

Bit(s)

Bit Name

Description

Default

Access

[7:4]

SI_VCO_SEL

Selects Core when Test Mode is Enabled.

0x0

R/W

0: all cores off.

1: VCO Core D.

10: VCO Core C.

100: VCO Core B.

1000: VCO Core A.

[3:0]

SI_VCO_BIAS_CODE

Sets VCO Bias when Test Mode is Enabled.

0x0

R/W

0000: maximum VCO bias (approximately 3.2 V).

1111: minimum VCO bias (approximately 1.8 V).

Address: 0x39, Default: 0x07, Name: REG0039

Select VCO VTUNE Target Voltage

when Tes t Mode is Enabled.

VCO Tes t Mux Select.

[7] RESERVED

[3:0] SI_VTUNE_CAL_SET (R/W)

[6:4] VCO_FSM_TEST_MUX_SEL (R/W)

Table 43. Bit Descriptions for REG0039

Bit(s)

Bit Name

Description

Default

Access

RESERVED

Reserved.

0x0

[6:4]

VCO_FSM_TEST_MUX_SEL

VCO Test Mux Select.

0x0

R/W

0: busy.

1: N band.

10: R band.

11: reserved.

100: timeout clock.

ADF4401ABCEZ Datasheet(PDF) 34 Page - Analog Devices

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