| Electronic Components Datasheet Search |
|
ADF4401ABCEZ Datasheet(PDF) 37 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADF4401ABCEZ Datasheet(HTML) 37 Page - Analog Devices |
|
37 / 39 page ![]() Data Sheet ADF4401A Rev. 0 | Page 37 of 39 Address: 0x6E, Default: 0x00, Name: REG006E Open-Loop VCO Counter Readback. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] VCO_DATA_READBACK[7:0] (R) Table 51. Bit Descriptions for REG006E Bit(s) Bit Name Description Default Access [7:0] VCO_DATA_READBACK[7:0] Open-Loop VCO Counter Readback. 0x0 R Address: 0x6F, Default: 0x00, Name: REG006F Open-Loop VCO Counter Readback. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] VCO_DATA_READBACK[15:8] (R) Table 52. Bit Descriptions for REG006F Bit(s) Bit Name Description Default Access [7:0] VCO_DATA_READBACK[15:8] Open-Loop VCO Counter Readback. 0x0 R Address: 0x72, Default: 0x32, Name: REG0072 Internal RF Output Frequency Select. Power-Down Internal RF Buffer. Internal RF Output Power. 0 0 1 1 2 0 3 0 4 1 5 1 6 0 7 0 [7] RESERVED [2:0] RESERVED [6] AUX_FREQ_SEL (R/W) [3] PDB_AUX (R/W) [5:4] POUT_AUX (R/W) Table 53. Bit Descriptions for REG0072 Bit(s) Bit Name Description Default Access 7 RESERVED Reserved. 0x0 R 6 AUX_FREQ_SEL Internal RF Output Frequency Select. This selects the VCO fundamental or divided frequency to the downconversion mixer. 0x0 R/W 0: divided output. 1: VCO output. [5:4] POUT_AUX Internal RF Output Power. Sets the power at the auxiliary RF port, which drives the mixer path. 0x1 R/W 0: low power. 1: high power. 3 PDB_AUX Power-Down Internal RF Buffer. This must be set to 1 for normal operation. 0x1 R/W [2:0] RESERVED Reserved. 0x2 R Address: 0x73, Default: 0x00, Name: REG0073 Lock Detector Count Divider. Dis able ADC clock. Power-Down N divider. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:3] RESERVED [0] LD_DIV (R/W) [2] ADC_CLK_DISABLE (R/W) [1] PD_NDIV (R/W) Table 54. Bit Descriptions for REG0073 Bits Bit Name Description Default Access [7:3] RESERVED Reserved. 0x0 R 2 ADC_CLK_DISABLE Disable ADC Clock. ADC_ENABLE setting overwrites this bit. 0x0 R/W 1 PD_NDIV Power-Down N Divider. 0x0 R/W 0 LD_DIV Lock Detector Count Divider. Divides the lock detector count cycles by 32 so that the LD_COUNT bits in the REG0028 register can be selected as 32, 64, 128, and 256. 0x0 R/W |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |