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ADF4401ABCEZ Datasheet(PDF) 24 Page - Analog Devices |
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ADF4401ABCEZ Datasheet(HTML) 24 Page - Analog Devices |
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24 / 39 page ![]() ADF4401A Data Sheet Rev. 0 | Page 24 of 39 Address: 0x10, Default: 0x32, Name: REG0010 16-Bit Integer Word. 0 0 1 1 2 0 3 0 4 1 5 1 6 0 7 0 [7:0] BIT_INTEGER_WORD[7:0] (R/W) Table 11. Bit Descriptions for REG0010 Bit(s) Bit Name Description Default Access [7:0] BIT_INTEGER_WORD[7:0] 16-Bit Integer Word. Sets the integer value of N (for the internal PLL). Updates to the PLL N counter, including FRAC1, FRAC2, and MOD2, are double buffered by this bit field. 0x32 R/W Address: 0x11, Default: 0x00, Name: REG0011 16-Bit Integer Word. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] BIT_INTEGER_WORD[15:8] (R/W) Table 12. Bit Descriptions for REG0011 Bit(s) Bit Name Description Default Access [7:0] BIT_INTEGER_WORD[15:8] 16-Bit Integer Word. Sets the integer value of N. 0x0 R/W Address: 0x12, Default: 0x40, Name: REG0012 Enables Autocalibration. Pres caler Select. 0 0 1 0 2 0 3 0 4 0 5 0 6 1 7 0 [7] RESERVED [4:0] RESERVED [6] EN_AUTOCAL (R/W) [5] PRE_SEL (R/W) Table 13. Bit Descriptions for REG0012 Bit(s) Bit Name Description Default Access 7 RESERVED Reserved. 0x0 R 6 EN_AUTOCAL Enables Autocalibration. 0x1 R/W 0: VCO autocalibration disabled. 1: VCO autocalibration enabled. 5 PRE_SEL Prescaler Select. The dual modulus prescaler for the calibration PLL is set by the PRE_SEL bit. The prescaler, at the input to the N divider, divides down the VCO signal so the N divider can handle it. The prescaler setting affects the RF frequency and the minimum and maximum INT values. 0x0 R/W 0: 4/5 prescaler. 1: 8/9 prescaler. [4:0] RESERVED Reserved. 0x0 R Address: 0x14, Default: 0x00, Name: REG0014 25-Bit FRAC1 Value. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] FRAC1WORD[7:0] (R/W) Table 14. Bit Descriptions for REG0014 Bit(s) Bit Name Description Default Access [7:0] FRAC1WORD[7:0] 25-Bit FRAC1 Value. Sets the FRAC1 value. 0x0 R/W |
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