ADF4401ABCEZ datasheet(18/39 Pages) AD

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ADF4401A

Data Sheet

Rev. 0 | Page 18 of 39

APPLICATIONS INFORMATION

DEVICE SETUP

The recommended sequence of steps to set up the ADF4401A

are as follows:

1. Set up the SPI.

2. Perform the initialization sequence.

3. Perform the frequency update sequence for the internal PLL.

4. Change the mode from internal PLL to external PFD.

5. Perform the frequency update sequence for the translation

loop.

Step 1: Set Up the SPI

Initialize the SPI. Write the values in Table 7 to the REG0000

Table 7. SPI Setup

Address

Setting

Notes

0x00

0x18

4-wire SPI

0x01

0x00

Stalling, master readback control

Step 2: Initialization Sequence

Write to each register in reverse order from Address 0x7C to

Address 0x10. Select the appropriate values to generate the

desired frequency. The frequency update sequence follows to

generate the desired output frequency.

Step 3: Frequency Update Sequence (Internal PLL)

Frequency updates require updating MOD2, FRAC1, FRAC2,

and INT. Therefore, the update sequence must be as follows:

1. REG001A (new MOD2WORD[13:8])

2. REG0019 (new MOD2WORD[7:0])

3. REG0018 (new FRAC2WORD[13:7])

4. REG0017 (new FRAC2WORD[6:0])

5. REG0016 (new FRAC1WORD[23:16])

6. REG0015 (new FRAC1WORD[15:8])

7. REG0014 (new FRAC1WORD[7:0])

8. REG0011 (new BIT_INTEGER_WORD[15:8])

9. REG0010 (new BIT_INTEGER_WORD[7:0])

The frequency change occurs on the write to the REG0010

The unchanged registers do not need to be updated. For example,

for an integer N PLL configuration (fractional parts are not

used), skip Step 1 to Step 7. In this case, the only required

updates are the REG0011 register and REG0010 register.

Step 4: External PFD Operation

The VTUNE input is switched to the external PFD and the

VCO locks using the translation loop module.

To improve performance, it is recommended to power off the

internal PLL synthesizer by setting REG001E, Bit 2 = 1.

Alternatively, if the switching speed between frequencies is to

be minimized, leave the internal PLL powered up and take the

following steps:

1. Place the internal PLL charge pump in tristate. REG003E,

Bits[3:2] = 0.

2. Disable the fractional-N Σ-Δ engine, REG002B, Bit 0 = 1.

3. Set the R divider to 0. REG001F, Bits[4:0] = 0.

4. Set the N divider to the maximum value, 65535. REG0010,

Bits[7:0] = 255 and REG0011, Bits[7:0] = 255.

Step 5: Frequency Update Sequence (Translation Loop)

Change the external PFD frequency and external LO frequency,

if required. Frequency updates require reenabling the internal

PFD, switching VTUNE to use the internal PFD, and locking

the VCO with the new frequency. Then, the VTUNE input is

switched to the external PFD, and the VCO locks to the new

frequency using the translation loop module.

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