MPF7100BVBA0ES datasheet(39/125 Pages) NXP

39 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

39 / 125

aaa-028061

RESETBMCU

REG4_PG

REG3_PG

REG2_PG

Reg Power down

2 ms (max)

Recovery

REG4

REG3

REG2

REG1_PG

REG1

PGOOD

(optional)

Figure 17. Power up sequencer aborted as fault persists for longer than 2.0 ms

Supplies enabled after RESETBMCU are checked for OV, UV, and ILIM faults after each

of them is enabled. If an OV, UV or ILIM condition is present, the PF7100 starts a fault

detection and protection mechanism as described in Section 14.7 "Fault detection". At

this point, the MCU should be able to read the interrupt and react upon a fault event as

defined by the system.

When OTP_PG_CHECK = 1, if PGOOD is used as a GPIO, it may be released at any

time in the power up sequence as long as the RESETBMCU is released after one or

more of the SW or LDO regulators.

If a regulator fault occurs after RESETBMCU is de-asserted but before the power

up sequence is finalized, the power up sequence continues to turn on the remaining

regulators as configured, even if a fault detection mechanism is active on an earlier

regulator.

14.8 Interrupt management

The MCU is notified of any interrupt through the INTB pin and various interrupt registers.

The interrupt registers are composed by three types of bits to help manage all the

interrupt request in the PF7100:

• The interrupt latch XXXX_I: this bit is set when the corresponding interrupt event

occurs. It can be read at any time, and is cleared by writing a 1 to the bit.

• The mask bit XXXX_M: this bit controls whether a given interrupt latch pulls the INTB

pin low or not.

• When the mask bit is 1, the interrupt latch does not control the INTB pin.

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