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MPF7100BVBA0ES Datasheet(PDF) 95 Page - NXP Semiconductors |
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MPF7100BVBA0ES Datasheet(HTML) 95 Page - NXP Semiconductors |
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95 / 125 page  NXP Semiconductors PF7100 7-channel power management integrated circuit for high performance applications PF7100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 9 March 2021 95 / 125 The device ID register provides general information about the PMIC. • DEVICE_FAM[3:0]: indicates the PF7100 family of devices 1000 (fixed) • DEVICE_ID[3:0]: provides the device type identifier 0000 = PF7100 Auto QM 1000 = PF7100 Auto ASIL B Registers 0x02 and 0x03 provide a customizable program ID registers to identify the specific OTP configuration programmed in the part. • EMREV (Address 0x02): contains the MSB bits PROG_ID[8:11] • PROG_ID (Address 0x03): contains the LSB bit PROG_ID[7:0] 16.1 PF7100 ASIL B functional register map RESET SIGNALS R/W types UVDET Reset when VIN crosses UVDET threshold R Read only OFF_OTP Bits are loaded with OTP values (mirror register) R/W Read and Write OFF_TOGGLE Reset when device goes to OFF mode RW1C Read, Write a 1 to clear SC Self-clear after write R/SW Read/Secure Write NO_VSNVS Reset when BOS has no valid input VIN < UVDET R/TW Read/Write on TBB only AD DR Register Name R/W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 00 DEVICE ID R DEVICE_FAM[3:0] DEVICE_ID[3:0] 01 REV ID R FULL_LAYER_REV[3:0] METAL_LAYER_REV[3:0] 02 EMREV R PROG_IDH[11:8] — EMREV[2:0] 03 PROG ID R PROG_IDL[7:0] 04 INT STATUS1 RW1C SDWN_I FREQ_RDY_I CRC_I PWRUP_I PWRDN_I XINTB_I FSOB_I VIN_OVLO_I 05 INT MASK1 R/W SDWN_M FREQ_RDY_M CRC_M PWRUP_M PWRDN_M XINTB_M FSOB_M VIN_OVLO_M 06 INT SENSE1 R — — — — — XINTB_S FSOB_S VIN_OVLO_S 07 THERM INT RW1C WDI_I FSYNC_FLT_I THERM_155_I THERM_140_I THERM_125_I THERM_110_I THERM_95_I THERM_80_I 08 THERM MASK R/W WDI_M FSYNC_FLT_M THERM_155_M THERM_140_M THERM_125_M THERM_110_M THERM_95_M THERM_80_M 09 THERM SENSE R WDI_S FSYNC_FLT_S THERM_155_S THERM_140_S THERM_125_S THERM_110_S THERM_95_S THERM_80_S 0A SW MODE INT RW1C — SW5_MODE_I — — SW4_MODE_I SW3_MODE_I SW2_MODE_I SW1_MODE_I 0B SW MODE MASK R/W — SW5_MODE_M — — SW4_MODE_M SW3_MODE_M SW2_MODE_M SW1_MODE_M 12 SW ILIM INT RW1C — SW5_ILIM_I — — SW4_ILIM_I SW3_ILIM_I SW2_ILIM_I SW1_ILIM_I 13 SW ILIM MASK R/W — SW5_ILIM_M — — SW4_ILIM_M SW3_ILIM_M SW2_ILIM_M SW1_ILIM_M 14 SW ILIM SENSE R — SW5_ILIM_S SW4_ILIM_S SW3_ILIM_S SW2_ILIM_S SW1_ILIM_S 15 LDO ILIM INT RW1C — — — — — — LDO2_ILIM_I LDO1_ILIM_I 16 LDO ILIM MASK R/W — — — — — — LDO2_ILIM_M LDO1_ILIM_M 17 LDO ILIM SENSE R — — — — — — LDO2_ILIM_S LDO1_ILIM_S 18 SW UV INT RW1C — SW5_UV_I — — SW4_UV_I SW3_UV_I SW2_UV_I SW1_UV_I 19 SW UV MASK R/W — SW5_UV_M — — SW4_UV_M SW3_UV_M SW2_UV_M SW1_UV_M 1A SW UV SENSE R — SW5_UV_S — — SW4_UV_S SW3_UV_S SW2_UV_S SW1_UV_S 1B SW OV INT RW1C — SW5_OV_I — — SW4_OV_I SW3_OV_I SW2_OV_I SW1_OV_I 1C SW OV MASK R/W — SW5_OV_M — — SW4_OV_M SW3_OV_M SW2_OV_M SW1_OV_M 1D SW OV SENSE R — SW5_OV_S — — SW4_OV_S SW3_OV_S SW2_OV_S SW1_OV_S 1E LDO UV INT RW1C — — — — — — LDO2_UV_I LDO1_UV_I 1F LDO UV MASK R/W — — — — — — LDO2_UV_M LDO1_UV_M 20 LDO UV SENSE R — — — — — — LDO2_UV_S LDO1_UV_S 21 LDO OV INT RW1C — — — — — — LDO2_OV_I LDO1_OV_I |
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