MCF5373CAB180 datasheet(18/46 Pages) NXP

18 / 46 page

MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4

Electrical Characteristics

Freescale Semiconductor

5.6

External Interface Timing Characteristics

Table 9 lists processor bus input timings.

NOTE

All processor bus timings are synchronous; that is, input setup/hold and output delay with

respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.

All other timing relationships can be derived from these values. Timings listed in Table 9

are shown in Figure 7 and Figure 8.

Discrete load capacitance for EXTAL

CL_EXTAL

2*CL–-

CS_EXTAL –

CPCB_EXTAL

CLKOUT Period Jitter, 3, 4, 7, 8, 9 Measured at fSYS Max

Peak-to-peak Jitter (Clock edge to clock edge)

Long Term Jitter

Cjitter

—

TBD

% fsys/3

Frequency Modulation Range Limit 3, 10, 11

(fsysMax must not be exceeded)

Cmod

0.8

2.2

%fsys/3

VCO Frequency. fvco = (fref * PFD)/4

fvco

350

540

MHz

1 The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock

frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.

2 All internal registers retain data at 0 Hz.

3 This parameter is guaranteed by characterization before qualification rather than 100% tested.

4 Proper PC board layout procedures must be followed to achieve specifications.

5 This parameter is guaranteed by design rather than 100% tested.

6 This specification is the PLL lock time only and does not include oscillator start-up time.

7 C

PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

8 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

sys.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.

Noise injected into the PLL circuitry via PLL VDD, EVDD, and VSS and variation in crystal oscillator frequency increase

the Cjitter percentage for a given interval.

9 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.

10 Modulation percentage applies over an interval of 10

μs, or equivalently the modulation rate is 100 KHz.

11 Modulation range determined by hardware design.

Table 8. PLL Electrical Characteristics (continued)

Num

Characteristic

Symbol

Min.

Value

Max.

Value

Unit

MCF5373CAB180 Datasheet(PDF) 18 Page - NXP Semiconductors

MCF5373CAB180 Datasheet(HTML) 18 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL