MCF5373CAB180 datasheet(31/46 Pages) NXP

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Electrical Characteristics

MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor

5.13

Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V.

5.13.1

MII Receive Signal Timing

The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency

must exceed twice the FEC_RXCLK frequency.

Table 18 lists MII receive channel timings.

Figure 18 shows MII receive signal timings listed in Table 18.

Figure 18. MII Receive Signal Timing Diagram

5.13.2

MII Transmit Signal Timing

Table 19 lists MII transmit channel timings.

The transmitter functions correctly up to a FEC_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency

must exceed twice the FEC_TXCLK frequency.

Figure 19 shows MII transmit signal timings listed in Table 19.

Table 18. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup

—

FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold

—

FEC_RXCLK pulse width high

35%

65%

FEC_RXCLK period

FEC_RXCLK pulse width low

35%

65%

FEC_RXCLK period

Table 19. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER invalid

—

FEC_TXCLK to FEC_TXD[3:0], FEC_TXEN, FEC_TXER valid

—

FEC_TXCLK pulse width high

35%

65%

FEC_TXCLK period

FEC_TXCLK pulse width low

35%

65%

FEC_TXCLK period

FEC_RXCLK (input)

FEC_RXD[3:0] (inputs)

FEC_RXDV

FEC_RXER

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