MCF5373CAB180 datasheet(23/46 Pages) NXP

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Electrical Characteristics

MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4

Freescale Semiconductor

Figure 10. SDR Read Timing

5.7.2

DDR SDRAM AC Timing Characteristics

When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive

data onto the memory bus. All timing numbers are relative to the four DQS byte lanes.

Table 11. DDR Timing Specifications

Num

Characteristic

Symbol

Min

Max

Unit

•

Frequency of Operation

tDDCK

Mhz

DD1

Clock Period1

tDDSK

12.5

16.67

DD2

Pulse Width High2

tDDCKH

0.45

0.55

SD_CLK

DD3

Pulse Width Low3

tDDCKL

0.45

0.55

SD_CLK

DD4

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Valid3

tSDCHACV

—

0.5

× SD_CLK

+1.0

DD5

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Hold

tSDCHACI

2.0

—

DD6

Write Command to first DQS Latching Transition

tCMDVDQ

—

1.25

SD_CLK

DD7

Data and Data Mask Output Setup (DQ-->DQS) Relative

to DQS (DDR Write Mode)4, 5

tDQDMV

1.5

—

SD_CLK

SD_CSn,

SDDM

D[31:0]

A[23:0],

SD_RAS,

SD_BA[1:0]

CMD

ROW

SD1

SD4

COL

WD1

WD2

WD3

WD4

SD9

3/4 MCLK

SD_SDR_DQS

SD_DQS[3:2]

Delayed

SD10

SD7

Board Delay

SD8

Board Delay

SD6

tDQS

Reference

SD_CLK

from

Memories

(Measured at Output Pin)

(Measured at Input Pin)

SD5

NOTE: Data driven from memories relative

to delayed memory clock.

SD_WE

SD_CAS,

SD2

SD3

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