MCF5373CAB180 datasheet(24/46 Pages) NXP

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MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4

Electrical Characteristics

Freescale Semiconductor

DD8

Data and Data Mask Output Hold (DQS-->DQ) Relative to

DQS (DDR Write Mode)6

tDQDMI

1.0

—

DD9

Input Data Skew Relative to DQS (Input Setup)7

tDVDQ

—1

DD10

Input Data Hold Relative to DQS8

tDIDQ

0.25

× SD_CLK

+0.5ns

—ns

DD11 DQS falling edge from SDCLK rising (output hold time)

tDQLSDCH

0.5

—

DD12 DQS input read preamble width

tDQRPRE

0.9

1.1

SD_CLK

DD13 DQS input read postamble width

tDQRPST

0.4

0.6

SD_CLK

DD14 DQS output write preamble width

tDQWPRE

0.25

SD_CLK

DD15 DQS output write postamble width

tDQWPST

0.4

0.6

SD_CLK

1 SD_CLK is one SDRAM clock in (ns).

2 Pulse width high plus pulse width low cannot exceed min and max clock period.

3 Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process, temperature,

and voltage variations.

4 This specification relates to the required input setup time of today’s DDR memories. The processor’s output setup should be

larger than the input setup of the DDR memories. If it is not larger, the input setup on the memory is in violation.

MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to

MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].

5 The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are

valid for each subsequent DQS edge.

6 This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],

MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative

MEM_DQS[0].

7 Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line

becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other

factors).

8 Data input hold is derived from each DQS clock edge. It begins with a DQS transition and ends when the first data line

becomes invalid.

Table 11. DDR Timing Specifications (continued)

Num

Characteristic

Symbol

Min

Max

Unit

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