AD7124-4TRUZ-EP-R7 datasheet(4/17 Pages) AD

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AD7124-4-EP

Enhanced Product

Rev. 0 | Page 4 of 17

SPECIFICATIONS

AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V,

REFINx(+) = 2.5 V, REFINx(−) = AVSS, master clock = 614.4 kHz, all specifications TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

ADC

Output Data Rate, fADC

Low Power Mode

1.17

2400

SPS

Mid Power Mode

2.34

4800

SPS

Full Power Mode

9.38

19,200

SPS

No Missing Codes2

Bits

FS3 > 2, sinc4 filter

Bits

FS3 > 8, sinc3 filter

Resolution

RMS Noise and Update Rates

Integral Nonlinearity (INL)

−4

±1

ppm of FSR

Gain = 12

−15

±2

+15

ppm of FSR

Gain > 14

Offset Error5

Before Calibration

±15

μV

Gain = 1 to 8

200/gain

μV

Gain = 16 to 128

After Internal Calibration/System

Calibration

In order of

noise

Offset Error Drift vs. Temperature6

Low Power Mode

nV/°C

Gain = 1 or gain > 16

nV/°C

Gain = 2 to 8

nV/°C

Gain = 16

Mid Power Mode

nV/°C

Gain = 1 or gain > 16

nV/°C

Gain = 2 to 8

nV/°C

Gain = 16

Full Power Mode

nV/°C

Gain Error5, 7

Before Internal Calibration

−0.0025

+0.0025

Gain = 1, TA = 25°C

−0.3

Gain > 1

After Internal Calibration

−0.016

+0.004

+0.016

Gain = 2 to 8, TA = 25°C

±0.025

Gain = 16 to 128

After System Calibration

In order of

noise

Gain Error Drift vs. Temperature

ppm/°C

Power Supply Rejection

AIN = 1 V/gain, external reference

Low Power Mode

Gain = 2 to 16

Gain = 1 or gain > 16

Mid Power Mode2

Gain = 2 to 16

100

Gain = 1 or gain > 16

Full Power Mode

Common-Mode Rejection8

At DC2

AIN = 1 V, gain = 1

105

115

AIN = 1 V/gain, gain 2 or 4

1029, 2

AIN = 1 V/gain, gain 2 or 4

115

120

AIN = 1 V/gain, gain ≥ 8

1059, 2

AIN = 1 V/gain, gain ≥ 8

Sinc3, Sinc4 Filter2

At 50 Hz, 60 Hz

120

10 SPS, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz

At 50 Hz

120

50 SPS, 50 Hz ± 1 Hz

At 60 Hz

120

60 SPS, 60 Hz ± 1 Hz

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