Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

AD7124-4TRUZ-EP-R7 Datasheet(PDF) 9 Page - Analog Devices

Part # AD7124-4TRUZ-EP-R7
Description  4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
PDF  17 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7124-4TRUZ-EP-R7 Datasheet(HTML) 9 Page - Analog Devices

Back Button AD7124-4TRUZ-EP-R7 Datasheet HTML 5Page - Analog Devices AD7124-4TRUZ-EP-R7 Datasheet HTML 6Page - Analog Devices AD7124-4TRUZ-EP-R7 Datasheet HTML 7Page - Analog Devices AD7124-4TRUZ-EP-R7 Datasheet HTML 8Page - Analog Devices AD7124-4TRUZ-EP-R7 Datasheet HTML 9Page - Analog Devices AD7124-4TRUZ-EP-R7 Datasheet HTML 10Page - Analog Devices AD7124-4TRUZ-EP-R7 Datasheet HTML 11Page - Analog Devices AD7124-4TRUZ-EP-R7 Datasheet HTML 12Page - Analog Devices AD7124-4TRUZ-EP-R7 Datasheet HTML 13Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 17 page
background image
Enhanced Product
AD7124-4-EP
Rev. 0 | Page 9 of 17
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
POWER-DOWN CURRENTS13
Independent of power mode
Standby Current
IAVDD
7
15
μA
LDOs on only
IIOVDD
8
20
μA
Power-Down Current
IAVDD
1
3
μA
IIOVDD
1
2
μA
1 Temperature range = −55°C to +125°C.
2 These specifications are not production tested but are supported by characterization data at the initial product release.
3 FS is the decimal equivalent of the FS[10:0] bits in the filter registers.
4 The integral nonlinearity is production tested in full power mode only. For other power modes, the specification is supported by characterization data at the initial
product release.
5 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
6 Recalibration at any temperature removes these errors.
7 Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1, TA = 25°C.
8 When gain > 1, the common-mode voltage is between (AVSS + 0.1 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).
9 Specification is for a wider common-mode voltage between (AVSS − 0.05 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).
10 REJ60 is a bit in the filter registers. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz and
60 Hz rejection.
11 When the gain is greater than 1, the analog input buffers are enabled automatically. The buffers can only be disabled when the gain equals 1.
12 When VREF = (AVDD − AVSS), the typical differential input equals 0.92 × VREF/gain for the low and mid power modes and 0.86 × VREF/gain for full power mode when gain > 1.
13 The digital inputs are equal to IOVDD or DGND with excitation currents and bias voltage generator disabled.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com