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AD7124-4TRUZ-EP-R7 Datasheet(PDF) 8 Page - Analog Devices

Part # AD7124-4TRUZ-EP-R7
Description  4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference
PDF  17 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7124-4TRUZ-EP-R7 Datasheet(HTML) 8 Page - Analog Devices

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AD7124-4-EP
Enhanced Product
Rev. 0 | Page 8 of 17
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC OUTPUTS (INCLUDING CLK)
Output Voltage2
High, VOH
IOVDD
− 0.35
V
ISOURCE = 100 μA
Low, VOL
0.4
V
ISINK = 100 μA
Floating State Leakage Current
−1
+1
μA
Floating State Output Capacitance
10
pF
Data Output Coding
Offset binary
SYSTEM CALIBRATION2
Calibration Limit
Full Scale (FS)
1.05 × FS
V
Zero Scale
−1.05 × FS
V
Input Span
0.8 × FS
2.1 × FS
V
POWER SUPPLY VOLTAGES FOR ALL POWER
MODES
AVDD to AVSS
Low Power Mode
2.7
3.6
V
Mid Power Mode
2.7
3.6
V
Full Power Mode
2.9
3.6
V
IOVDD to GND
1.65
3.6
V
AVSS to GND
−1.8
0
V
IOVDD to AVSS
5.4
V
POWER SUPPLY CURRENTS11, 13
IAVDD, External Reference
Low Power Mode
Gain = 12
125
140
μA
All buffers off
Gain = 1 IAVDD Increase per AINx Buffer2
15
25
μA
Gain = 2 to 8
205
250
μA
Gain = 16 to 128
235
300
μA
IAVDD Increase per Reference Buffer2
10
20
μA
All gains
Mid Power Mode
Gain = 12
150
170
μA
All buffers off
Gain = 1 IAVDD Increase per AINx Buffer2
30
40
μA
Gain = 2 to 8
275
345
μA
Gain = 16 to 128
330
430
μA
IAVDD Increase per Reference Buffer2
20
30
μA
All gains
Full Power Mode
Gain = 12
315
350
μA
All buffers off
Gain = 1 IAVDD Increase per AINx Buffer2
90
135
μA
Gain = 2 to 8
660
830
μA
Gain = 16 to 128
875
1200
μA
IAVDD Increase per Reference Buffer2
85
120
μA
All gains
IAVDD Increase
Due to Internal Reference2
50
70
μA
Independent of power mode; the
reference buffers are not required
when using this reference
Due to VBIAS2
15
20
μA
Independent of power mode
Due to Diagnostics2
4
5
μA
IIOVDD
Low Power Mode
20
35
μA
Mid Power Mode
25
40
μA
Full Power Mode
55
80
μA



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