Enhanced Product

AD7124-4-EP

Rev. 0 | Page 11 of 17

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

20

21

22

23

24

19

18

17

16

15

14

13

12

11

SCLK

CLK

CS

DGND

REGCAPD

DIN

SYNC

PSW

REFOUT

REGCAPA

AIN0/IOUT/VBIAS

AIN1/IOUT/VBIAS

REFIN1(+)

AIN3/IOUT/VBIAS/P2

AIN2/IOUT/VBIAS/P1

AIN7/IOUT/VBIAS/REFIN2(–)

AIN6/IOUT/VBIAS/REFIN2(+)

REFIN1(–)

AIN4/IOUT/VBIAS

AIN5/IOUT/VBIAS

DOUT/RDY

AD7124-4-EP

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

DIN

Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to

the control registers within the ADC, with the register selection bits of the communications register

identifying the appropriate register.

2

SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous

with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock

with the information being transmitted to or from the ADC in smaller batches of data.

3

CLK

Clock Input/Clock Output. The internal clock can be made available at this pin. Alternatively, the internal

clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be

driven from a common clock, allowing simultaneous conversions to be performed.

4

CS

Chip Select Input. This is an active low logic input that selects the ADC. Use CS to select the ADC in systems

with more than one device on the serial bus or as a frame synchronization signal in communicating with the

device. CS can be hardwired low if the serial peripheral interface (SPI) diagnostics are unused, allowing the

ADC to operate in 3-wire mode with SCLK, DIN, and DOUT interfacing with the device.

5

REGCAPD

Digital LDO Regulator Output. Decouple this pin to DGND with a 0.1 μF capacitor.

6

7

DGND

Digital Ground Reference Point.

8

AIN0/IOUT/VBIAS

Analog Input 0/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

9

AIN1/IOUT/VBIAS

Analog Input 1/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

10

AIN2/IOUT/VBIAS/P1

Analog Input 2/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 1. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured