AD7124-4TRUZ-EP-R7 datasheet(12/17 Pages) AD

12 / 17 page

AD7124-4-EP

Enhanced Product

Rev. 0 | Page 12 of 17

Pin No.

Mnemonic

Description

AIN3/IOUT/VBIAS/P2

Analog Input 3/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 2. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AVSS and AVDD.

REFIN1(+)

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−).

REFIN1(+) can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference voltage (REFIN1(+) −

REFIN1(−)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD.

REFIN1(−)

Negative Reference Input. This reference input can be anywhere between AVSS and

AVDD – 0.5 V.

AIN4/IOUT/VBIAS

Analog Input 4/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

AIN5/IOUT/VBIAS

Analog Input 5/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

AIN6/IOUT/VBIAS/

REFIN2(+)

Analog Input 6/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. This

input pin is configured via the configuration registers to be the positive or negative terminal of a differential or

pseudo differential input. Alternatively, the internal programmable excitation current source can be made

available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between

the analog power supply rails can be generated at this pin. This pin also functions as a positive reference

input for REFIN2(±). REFIN2(+) can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference

voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the device functions with a reference from 0.5 V to AVDD.

AIN7/IOUT/VBIAS/

REFIN2(−)

Analog Input 7/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. This

input pin is configured via the configuration registers to be the positive or negative terminal of a differential or

pseudo differential input. Alternatively, the internal programmable excitation current source can be made

available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between

the analog power supply rails can be generated at this pin. This pin also functions as the negative reference

input for REFIN2(±). This reference input can be anywhere between AVSS and AVDD – 0.5 V.

REFOUT

Internal Reference Output. The buffered output of the internal 2.5 V voltage reference is available on this pin.

AVSS

Analog Supply Voltage. The voltage on AVDD is referenced to AVSS. The differential between AVDD and AVSS

must be between 2.7 V and 3.6 V in mid or low power mode and between 2.9 V and 3.6 V in full power

mode. AVSS can be taken below 0 V to provide a dual power supply to the AD7124-4-EP. For example, AVSS

can be tied to −1.8 V and AVDD can be tied to +1.8 V, providing a ±1.8 V supply to the ADC.

REGCAPA

Analog LDO Regulator Output. Decouple this pin to AVSS with a 0.1 μF capacitor.

PSW

Low-Side Power Switch to AVSS.

AVDD

Analog Supply Voltage, Relative to AVSS.

SYNC

Synchronization Input. This pin is a logic input that allows synchronization of the digital filters and analog

modulators when using a number of AD7124-4-EP devices. When SYNC is low, the nodes of the digital

filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is held

in a reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low.

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDY functions as a serial data output pin to access the

output shift register of the ADC. The output shift register can contain data from any of the on-chip data

or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion

of a conversion. If the data is not read after the conversion, the pin goes high before the next update

occurs. The DOUT/RDY falling edge can also be used as an interrupt to a processor, indicating that valid

data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. When CS is

low, the data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is

valid on the SCLK rising edge.

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