PIC18F1230-ESLASHML datasheet(78/312 Pages) MICROCHIP

78 / 312 page

PIC18F1230/1330

DS39758B-page 76

Advance Information

EECON1: EEPROM CONTROL REGISTER 1

R/W-x

U-0

R/W-0

R/W-x

R/W-0

R/S-0

EEPGD

CFGS

—

FREE

WRERR(1)

WREN

bit 7

bit 0

Legend:

S = Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

EEPGD: Flash Program or Data EEPROM Memory Select bit

= Access Flash program memory

= Access data EEPROM memory

bit 6

CFGS: Flash Program/Data EEPROM or Configuration Select bit

= Access Configuration registers

= Access Flash program or data EEPROM memory

bit 5

Unimplemented: Read as ‘0’

bit 4

FREE: Flash Row Erase Enable bit

= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

= Perform write-only

bit 3

WRERR: EEPROM Error Flag bit(1)

= A write operation is prematurely terminated

(MCLR or WDT Reset during self-timed erase or program operation)

= The write operation completed

bit 2

WREN: Erase/Write Enable bit

= Allows erase/write cycles

= Inhibits erase/write cycles

bit 1

WR: Write Control bit

= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete.

The WR bit can only be set (not cleared) in software.)

= Write cycle to is completed

bit 0

RD: Read Control bit

= Initiates a memory read. (Read takes one cycle. RD is cleared in hardware. The RD bit can only be

set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

= Read completed

Note 1:

When a WRERR occurs, the EEPGD or FREE bit is not cleared. This allows tracing of the error condition.

PIC18F1230-E/ML Datasheet(PDF) 78 Page - Microchip Technology

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