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PIC18F1230-E/ML Datasheet(PDF) 86 Page - Microchip Technology |
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PIC18F1230-E/ML Datasheet(HTML) 86 Page - Microchip Technology |
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86 / 312 page ![]() PIC18F1230/1330 DS39758B-page 84 Advance Information © 2006 Microchip Technology Inc. 9.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 9-2: INITIALIZING PORTB Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Pins RB0, RB1 and RB4:RB7 are multiplexed with the power control PWM outputs. Pins RB2 and RB3 are multiplexed with external interrupt inputs, interrupt-on-change input, the analog comparator inputs and the Timer1 oscillator input and output to become RB2/INT2/KBI2/CMP2/T1OSO/T1CKI and RB3/INT3/KNBI3/CMP1/T1OSI respectively. When the interrupt-on-change feature is enabled, only pins configured as inputs can cause this interrupt to occur (i.e., any RB2, RB3, RA0 and RA1 pin configured as an output is excluded from the interrupt-on-change comparison). The input pins (RB2, RB3, RA0 and RA1) are compared with the old value latched on the last read of PORTA and PORTB. The “mismatch” outputs of these pins are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from Sleep mode, or any of the Idle modes. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTA and/or PORTB (except with the MOVFF (ANY), PORTA and MOVFF (ANY), PORTB instructions). b) Clear flag bit, RBIF. A mismatch condition will continue to set flag bit, RBIF. Reading PORTA and PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTA and PORTB are used for the interrupt- on-change feature. Polling of PORTA and PORTB is not recommended while using the interrupt-on-change feature. Note: On a Power-on Reset, PORTB is configured as digital inputs except for RB2 and RB3. RB2 and RB3 are configured as analog inputs when the T1OSCMX bit of Configu- ration Register 3H is cleared. Otherwise, RB2 and RB3 are also configured as digital inputs. CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches CLRF LATB ; Alternate method ; to clear output ; data latches MOVLW 0Fh ; Set RB<4:0> as MOVWF ADCON1 ; digital I/O pins ; (required if config bit ; PBADEN is set) MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs |
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