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PIC18F1230-E/ML Datasheet(PDF) 84 Page - Microchip Technology |
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PIC18F1230-E/ML Datasheet(HTML) 84 Page - Microchip Technology |
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84 / 312 page  PIC18F1230/1330 DS39758B-page 82 Advance Information © 2006 Microchip Technology Inc. TABLE 9-1: PORTA I/O SUMMARY Pin Function TRIS Setting I/O I/O Type Description RA0/AN0/INT0/ KBI0/CMP0 RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA Analog input 0. INT0 1 I ST External interrupt 0. KBI0 1 I TTL Interrupt-on-change pin. CMP0 1 I ANA Comparator 0 input. RA1/AN1/INT1/ KBI1 RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA Analog input 1. INT1 1 I ST External interrupt 1. KBI1 1 I TTL Interrupt-on-change pin. RA2/TX/CK RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when CVREF output enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. TX 0 0 DIG EUSART asynchronous transmit. CK 0 O DIG EUSART synchronous clock. 1 IST RA3/RX/DT RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. RX 1 I ANA EUSART asynchronous receive. DT 0 O DIG EUSART synchronous data. 1 ITTL RA4/T0CKI/AN2/ VREF+ RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input; default configuration on POR. T0CKI 1 I ST Timer0 external clock input. AN2 1 I ANA Analog input 2. VREF+ 1 I ANA A/D reference voltage (high) input. MCLR/VPP/RA5/ FLTA MCLR 1 I ST Master Clear (Reset) input. This pin is an active-low Reset to the device. VPP 1 I ANA Programming voltage input. RA5 1 I ST Digital input. FLTA(1) 1 I ST Fault detect input for PWM. RA6/OSC2/CLKO/ T1OSO/T1CKI/AN3 RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. 1 I ST PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. OSC2 0 O ANA Oscillator crystal output or external clock source output. CLKO 0 O ANA Oscillator crystal output. T1OSO(2) 0 O ANA Timer1 oscillator output. T1CKI(2) 1 I ST Timer1 clock input. AN3 1 I ANA Analog input 3. RA7/OSC1/CLKI/ T1OSI/FLTA RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes. 1 I TTL PORTA<7> data input. Disabled in external oscillator modes. OSC1 1 I ANA Oscillator crystal input or external clock source input. CLKI 1 I ANA External clock source input. T1OSI(2) 1 I ANA Timer1 oscillator input. FLTA(1) 1 I ST Fault detect input for PWM. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. 2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H. |
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