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PIC18F1230-E/ML Datasheet(PDF) 95 Page - Microchip Technology |
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PIC18F1230-E/ML Datasheet(HTML) 95 Page - Microchip Technology |
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95 / 312 page  PIC18F1230/1330 © 2006 Microchip Technology Inc. Advance Information DS39758B-page 93 REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 OSCFIF — — EEIF —LVDIF — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred 0 = A low-voltage condition has not occurred bit 1-0 Unimplemented: Read as ‘0’ REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 — — —PTIF — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIF: PWM Time Base Interrupt bit 1 = PWM time base matched the value in PTPER register. Interrupt is issued according to the postscaler settings. PTIF must be cleared in software. 0 = PWM time base has not matched the value in PTPER register bit 3-0 Unimplemented: Read as ‘0’ |
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