GD25Q41ASIGT datasheet(31/51 Pages) GIGADEVICE

31 / 51 page

Uniform Sector

Dual and Quad Serial Flash

GD25Q21B

check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase

cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)

bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP4,BP3,BP2, BP1, BP0) bits are set to

“None

protected

”. The Chip Erase (CE) command is ignored if one or more sectors are protected.

Figure 24. Chip Erase Sequence Diagram

7.21.

Deep Power-Down (DP) (B9H)

Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode

(the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in

active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the

device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the

Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)

command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from

Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep

Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO.

The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby

Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS#

must be driven low for the entire duration of the sequence.

The Deep Power-Down command sequence: CS# goes low  sending Deep Power-Down command  CS# goes

high. The command sequence is shown in Figure25. CS# must be driven high after the eighth bit of the command code has

been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it

requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep

Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects

on the cycle that is in progress.

Figure 25. Deep Power-Down Sequence Diagram

7.22.

Release from Deep Power-Down or High Performance Mode and Read

Device ID (RDI) (ABH)

The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can be

used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic

identification (ID) number.

Command

60H or C7H

CS#

SCLK

Command

B9H

CS#

SCLK

tDP

Stand-by mode Deep Power-down mode

GD25Q41ASIGT Datasheet(PDF) 31 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25Q41ASIGT Datasheet(HTML) 31 Page - GigaDevice Semiconductor (Beijing) Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL