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GD25Q41ASIGT Datasheet(PDF) 41 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25Q41ASIGT Datasheet(HTML) 41 Page - GigaDevice Semiconductor (Beijing) Inc. |
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41 / 51 page ![]() Uniform Sector Dual and Quad Serial Flash GD25Q21B 41 8. ELECTRICAL CHARACTERISTICS 8.1. POWER-ON TIMING Vcc(max) Vcc(min) VWI Reset State tPUW tVSL Chip Selection is not allowed Program, Erase and Read command are ignored Device is fully accessible Time Table3. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min Typ Max Unit tVSL VCC(min) To CS# Low 5 ms tPUW Time Delay Before Write Instruction 5 10 ms VWI Write Inhibit Voltage 2.1 2.3 2.5 V 8.2. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register contains 00H (all Status Register bits are 0). 8.3. DATA RETENTION AND ENDURANCE Parameter Test Condition Min Units Minimum Pattern Data Retention Time 150℃ 10 Years 125℃ 20 Years Erase/Program Endurance -40 to 85℃ 100K Cycles 8.4. LATCH UP CHARACTERISTICS Parameter Min Max Input Voltage Respect To VSS On I/O Pins -1.0V VCC+1.0V VCC Current -100mA 100mA |
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