GD25Q41ASIGT datasheet(39/51 Pages) GIGADEVICE

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Uniform Sector

Dual and Quad Serial Flash

GD25Q21B

7.31.

Continuous Read Mode Reset (CRMR) (FFH)

The Dual/Quad I/O Fast Read operations,

“Continuous Read Mode” bits (M7-0) are implemented to further reduce

command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the

BBH/EBH/E7H command code.

If the system controller is reset during operation it will likely send a standard SPI command, such as Read ID (9FH) or

Fast Read (0BH), to the device. Because the GD25Q21B has no hardware reset pin, so if Continuous Read Mode bits are

set to

“AXH”, the GD25Q21B will not recognize any standard SPI commands. So Continuous Read Mode Reset command

will release the Continuous Read Mode from the

“AXH” state and allow standard SPI command to be recognized. The

command sequence is show below.

Figure 36. Continuous Read Mode Reset Sequence Diagram

7.32.

Program/Erase Suspend (PES) (75H)

The Erase/Program Suspend instruction

“75H”, allows the system to interrupt a sector/block erase or page program

operation and then read data from any other sector or block. The Write Status Register command (01H), Page

Command

48H

CS#

SCLK

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

MSB

34 35 36 37

38 39

Data Out1

42 43 44 45

46 47

Data Out2

CS#

SCLK

MSB

Dummy Byte

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

FFH

Mode Bit Reset for Quad/Dual I/O

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