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GD25Q41ASIGT Datasheet(PDF) 12 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25Q41ASIGT Datasheet(HTML) 12 Page - GigaDevice Semiconductor (Beijing) Inc. |
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12 / 51 page ![]() Uniform Sector Dual and Quad Serial Flash GD25Q21B 12 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available on special order. Please contact GigaDevice for details. QE bit. The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply or ground). HPF bit The High Performance Flag (HPF) bit indicates the status of High Performance Mode (HPM). When HPF bit sets to 1, it means the device is in High Performance Mode, when HPF bit sets 0 (default), it means the device is not in High Performance Mode. LB3, LB2, LB1, bits. The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One Time Programmable, once its set to 1, the Security Registers will become read-only permanently. CMP bit The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. SUS bit The SUS bit is read only bit in the status register (S15) that is set to 1 after executing an Erase/Program Suspend (75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down, power-up cycle. |
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