1ST040EH2F35I3VLS1 datasheet(9/39 Pages) INTEL

9 / 39 page

Feature

Description

• Fast lock-time support for Gigabit Passive Optical Networking (GPON) PCS

• 8B/10B, 64B/66B, 64B/67B encoders and decoders

• Custom mode support for proprietary protocols

Power management

• SmartVID controlled core voltage, standard power devices

High performance monolithic

core fabric

• Intel Hyperflex core architecture with Hyper-Registers everywhere throughout the

interconnect routing and at the inputs of all functional blocks

• Monolithic fabric minimizes compile times and increases logic utilization

• Enhanced adaptive logic module (ALM)

• Improved multi-track routing architecture reduces congestion and improves compile

times

• Hierarchical core clocking architecture with programmable clock tree synthesis

• Fine-grained partial reconfiguration

Internal memory blocks

• eSRAM - 47.25 Mbit blocks with hard ECC support, select devices

• M20K—20 Kb with hard ECC support

• MLAB—640 bit distributed LUTRAM

Variable precision DSP

blocks

• IEEE 754-compliant hard single-precision floating point capability

• Supports signal processing with precision ranging from 18x19 up to 54x54

• Native 27x27 and 18x19 multiply modes

• 64 bit accumulator and cascade for systolic FIRs

• Internal coefficient memory banks

• Pre-adder/subtractor improves efficiency

• Additional pipeline register increases performance and reduces power

Phase locked loops (PLL)

• Fractional synthesis PLLs (fPLL) support both fractional and integer modes

• Fractional mode with third-order delta-sigma modulation

• Precision frequency synthesis

• Integer PLLs adjacent to general purpose I/Os, support external memory, and LVDS

interfaces, clock delay compensation, zero delay buffering

Core clock networks

• 1 GHz fabric clocking

• 667 MHz external memory interface clocking, supports 2666 Mbps DDR4 interface

• 800 MHz LVDS interface clocking, supports 1600 Mbps LVDS interface

• Programmable clock tree synthesis, backwards compatible with global, regional and

peripheral clock networks

• Clocks only synthesized where needed, to minimize dynamic power

continued...

1. Intel® Stratix® 10 TX Device Overview

683717 | 2022.08.18

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1ST040EH2F35I3VLS1 Datasheet(PDF) 9 Page - Intel Corporation

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