1ST040EH2F35I3VLS1 datasheet(21/39 Pages) INTEL

21 / 39 page

KR4 Forward Error Correction (FEC) circuit. For highly customized implementations, a

PCS Direct mode provides an interface up to 64 bits wide to allow for custom encoding

and support for data rates up to 28.9 Gbps.

For more information about the PCS-Core interface or the double rate transfer mode,

refer to the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide, and the Intel

Stratix 10 E-Tile Transceiver PHY User Guide.

Table 8.

Transceiver PCS Features

PCS Protocol

Support

Data Rate (Gbps)

Transmitter Data Path

Receiver Data Path

Standard PCS

0.125 to 12.5

Phase compensation FIFO, byte

serializer, 8B/10B encoder, bit-slipper,

channel bonding

Rate match FIFO, word-aligner, 8B/10B

decoder, byte deserializer, byte

ordering

PCI Express

Gen1/Gen2 x1,

x2, x4, x8, x16

2.5 and 5.0

Same as Standard PCS plus PIPE 2.0

interface to core

Same as Standard PCS plus PIPE 2.0

interface to core

PCI Express Gen3

x1, x2, x4, x8,

x16

8.0

Phase compensation FIFO, byte

serializer, encoder, scrambler, bit-

slipper, gear box, channel bonding, and

PIPE 3.0 interface to core, auto speed

negotiation

Rate match FIFO (0-600 ppm mode),

word-aligner, decoder, descrambler,

phase compensation FIFO, block sync,

byte deserializer, byte ordering, PIPE

3.0 interface to core, auto speed

negotiation

CPRI

0.6144 to 9.8

Same as Standard PCS plus

deterministic latency serialization

Same as Standard PCS plus

deterministic latency deserialization

Enhanced PCS

2.5 to 17.4

FIFO, channel bonding, bit-slipper, and

gear box

FIFO, block sync, bit-slipper, and gear

box

10GBASE-R

10.3125

FIFO, 64B/66B encoder, scrambler,

FEC, and gear box

FIFO, 64B/66B decoder, descrambler,

block sync, FEC, and gear box

Interlaken

4.9 to 17.4

FIFO, channel bonding, frame

generator, CRC-32 generator,

scrambler, disparity generator, bit-

slipper, and gear box

FIFO, CRC-32 checker, frame sync,

descrambler, disparity checker, block

sync, and gear box

SFI-S/SFI-5.2

11.3

FIFO, channel bonding, bit-slipper, and

gear box

FIFO, bit-slipper, and gear box

IEEE 1588

1.25 to 10.3125

FIFO (fixed latency), 64B/66B encoder,

scrambler, and gear box

FIFO (fixed latency), 64B/66B decoder,

descrambler, block sync, and gear box

SDI

up to 12.5

FIFO and gear box

FIFO, bit-slipper, and gear box

GigE

1.25

Same as Standard PCS plus GigE state

machine

Same as Standard PCS plus GigE state

machine

PCS Direct

up to 28.9

Custom

Related Information

Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide

1.9. PCI Express Gen1/Gen2/Gen3 Hard IP

Intel Stratix 10 TX devices contain embedded PCI Express hard IP designed for

performance, ease-of-use, increased functionality, and designer productivity.

The PCI Express hard IP consists of the PHY, Data Link, and Transaction layers. It also

supports PCI Express Gen1/Gen2/Gen3 end point and root port, in x1/x2/x4/x8/x16

lane configurations. The PCI Express hard IP is capable of operating independently

1. Intel® Stratix® 10 TX Device Overview

683717 | 2022.08.18

Send Feedback

Intel® Stratix® 10 TX Device Overview

1ST040EH2F35I3VLS1 Datasheet(PDF) 21 Page - Intel Corporation

1ST040EH2F35I3VLS1 Datasheet(HTML) 21 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Datasheet Download

Link URL