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1ST040EH2F35I3VLS1 Datasheet(PDF) 3 Page - Intel Corporation |
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1ST040EH2F35I3VLS1 Datasheet(HTML) 3 Page - Intel Corporation |
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3 / 39 page ![]() 1. Intel® Stratix® 10 TX Device Overview Intel® Stratix® 10 TX FPGAs feature power-efficient, dual-mode transceivers, capable of both 57.8 Gbps PAM4 (Pulse Amplitude Modulation) and 28.9 Gbps NRZ (Non Return to Zero) operation. Supported by hardened PCI Express Gen 3 and 10/25/100 Gbps Ethernet MAC IP blocks, these devices can deliver over 8 Tbps of aggregate bandwidth, meeting the demanding transceiver bandwidth and power budget specifications of next generation designs. In addition to the 57.8 Gbps PAM4 / 28.9 Gbps NRZ dual-mode transceivers, Intel Stratix 10 TX devices feature several other breakthrough innovations. These include all new HyperFlex® core architecture, hardened floating point DSP blocks, hardened external memory controllers and advanced packaging technology based on Intel's Embedded Multi-die Interconnect Bridge (EMIB). With an embedded quad-core 64-bit Arm* Cortex*-A53 hard processor system (HPS) available in select devices, Intel Stratix 10 TX FPGAs deliver power efficient, application-class processing, and allow designers to extend hardware virtualization into the FPGA fabric. Intel Stratix 10 TX FPGAs integrate a monolithic 14 nm FPGA fabric die with multiple high-speed transceiver tiles, all inside a single flip-chip BGA package. This implementation, combined with the unmatched transceiver bandwidth and core fabric performance, demonstrates Intel's commitment to deliver high-performance programmable solutions to your most challenging system design problems. Important innovations in Intel Stratix 10 TX devices include: • All new Intel Hyperflex™ core architecture delivering 2X the core performance compared to previous generation high-performance FPGAs • Intel 14 nm tri-gate (FinFET) technology • Heterogeneous 3D System-in-Package (SiP) technology • Monolithic core fabric with up to 2.8 million logic elements (LEs) • Up to 144 full duplex transceiver channels on heterogeneous 3D SiP transceiver tiles • Transceiver data rates up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ for chip-to-chip, chip-to-module, and backplane applications • Embedded eSRAM (47.25 Mbit) in select devices, and M20K (20 Kb) internal SRAM memory blocks • Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops (PLLs) • Hard PCI Express® Gen3 x16 intellectual property (IP) blocks • Hard 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) 683717 | 2022.08.18 Send Feedback Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered |
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