Table 6.

Intel Stratix 10 TX Package Plan

Cell legend: General Purpose I/Os, High-Voltage I/Os, LVDS Pairs, E-tile Transceivers, H-tile Transceivers. (2) (3)

(4) (5) (6)

Intel Stratix

10 TX Device

Name

F1152

HF35 - 24 Transceivers

(35 x 35 mm2)

F1760

NF43 - 48 Transceivers

(42.5 x 42.5 mm2)

F2397

SF50 - 72 Transceivers

UF50 - 96 Transceivers

(50 x 50 mm2)

F2912

YF55 - 144 Transceivers

(55 x 55 mm2)

TX 400

384, 0, 144, 24, 0

-

-

-

TX 850

-

440, 8, 216, 24, 24

440, 8, 216, 48, 24

-

TX 1100

-

440, 8, 216, 24, 24

440, 8, 216, 48, 24

-

TX 1650

-

-

440, 8, 216, 72, 24

-

TX 2100

-

-

440, 8, 216, 72, 24

-

TX 2500

-

-

440, 8, 216, 72, 24

296, 8, 144, 120, 24

TX 2800

-

-

440, 8, 216, 72, 24

296, 8, 144, 120, 24

Figure 3.

Tile Configuration 1: HF35 Package

Package Substrate

Core Fabric

®

E-Tile

(24 Channels)

HF35 (F1152)

(2) All packages are ball grid arrays with 1.0 mm pitch.

(3) High-Voltage I/O pins are used for 3 V and 2.5 V interfacing.

(4) Each LVDS pair can be configured as either a differential input or a differential output.

(5) High-Voltage I/O pins and LVDS pairs are included in the General Purpose I/O count.

Transceivers are counted separately.

(6) Each package column offers pin migration (common circuit board footprint) for all devices in

the column.

1. Intel® Stratix® 10 TX Device Overview

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Intel® Stratix® 10 TX Device Overview

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