1ST040EH2F35I3VLS1 datasheet(39/39 Pages) INTEL

39 / 39 page

Version

Changes

• Added black key provisioning (-BK) devices. See the "Sample Ordering Code" figure in

Available Options.

2020.03.24

Made the following change:

• Added advanced security (-AS) devices.

2019.08.19

Made the following changes:

• Added composition details for the leaded and lead-free contact device options.

• Updated family plan device options and added a tile layout variant.

2019.03.11

Made the following changes:

• Updated maximum transceiver data rate from 30 Gbps to 28.9 Gbps.

2019.02.15

Made the following changes:

• Added "Figure 1: Sample Ordering Code and Available Options for Intel Stratix 10

Devices" in the "Intel Stratix 10 TX Devices" section.

• Changed the number of eSRAM memory block to 47.25 Mb and the number of

embedded memory to 94.5 Mb.

• Changed the number of maximum transceiver data rate to 57.8 Gbps.

• Added the resource availabilities for the TX 400, TX 650, TX 850, and TX 1100 devices

in the "Intel Stratix 10 TX Family Plan—FPGA Core (part 1)" table.

• Added the resource availabilities for the TX 400, TX 650, TX 850, and TX 1100 devices

in the "Intel Stratix 10 TX Family Plan - Interconnects, PLLs and Hard IP (part 1)" table.

• Added the resource availabilities for the TX 400, TX 650, TX 850, and TX 1100 devices

in the "Intel Stratix 10 TX Package Plan" table.

• Updated Tile Layout diagrams for NF43 (F1760) and SF50 (F2397) packages.

2018.08.10

Made the following changes:

• Changed the direction arrow from the coefficient registers block in the "DSP Block: High

Precision Fixed Point Mode" figure.

• Changed the descriptions for the core process technology and power management

features in the "Intel Stratix 10 TX Device Features" table.

• Changed the description of the SmartVID in the "Power Management" section.

2018.02.21

Made the following changes:

• Updated the fPLL counts in the "Intel Stratix 10 TX Family Plan - Interconnects, PLLs

and Hard IP (part 2)" table.

• Changed the fPLL counts in the "Fractional Synthesis and I/O PLLs" section.

2017.10.30

Made the following changes:

• Changed the resource availabilities for the TX 1650 and TX 2100 devices in the "Intel

Stratix 10 TX Family Plan—FPGA Core (part 1)" table.

2017.08.02

Made the following changes:

• Only some of the devices have eSRAM. Mentioned this in the appropriate places in the

app note

• 100Gbe Hard IP included in the bottom left H-tile of the Intel Stratix 10 TX Architecture

Block Diagram

• Added a new column "HPS" in the Intel Stratix 10 TX Family Plan - FPGA Core (part 1)

table

• Updated table "Intel Stratix 10 TX Family Plan - Interconnects, PLLs and Hard IP (part

2)"

• Added Tile Layout diagrams

2016.10.31

Initial release.

1. Intel® Stratix® 10 TX Device Overview

683717 | 2022.08.18

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Intel® Stratix® 10 TX Device Overview

1ST040EH2F35I3VLS1 Datasheet(PDF) 39 Page - Intel Corporation

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