Contents

1. Intel® Stratix® 10 TX Device Overview........................................................................... 3

1.1. Intel Stratix 10 TX Devices..................................................................................... 4

1.1.1. Available Options....................................................................................... 6

1.2. Innovations in Intel Stratix 10 TX Devices.................................................................6

1.3. Intel Stratix 10 TX Features Summary......................................................................8

1.4. Intel Stratix 10 TX Block Diagram.......................................................................... 11

1.5. Intel Stratix 10 TX Family Plan...............................................................................12

1.6. Intel Hyperflex Core Architecture........................................................................... 15

1.7. Heterogeneous 3D SiP Transceiver Tiles.................................................................. 17

1.8. Intel Stratix 10 TX Transceivers............................................................................. 18

1.8.1. PMA Features......................................................................................... 18

1.8.2. PCS Features..........................................................................................20

1.9. PCI Express Gen1/Gen2/Gen3 Hard IP....................................................................21

1.10. Ethernet MAC, Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals

(544, 514) ...................................................................................................... 22

1.11. 10G Ethernet Hard IP......................................................................................... 22

1.12. Interlaken PCS Hard IP....................................................................................... 22

1.13. External Memory and General Purpose I/O............................................................ 22

1.14. Adaptive Logic Module (ALM)............................................................................... 24

1.15. Core Clocking.................................................................................................... 25

1.16. Fractional Synthesis PLLs and I/O PLLs..................................................................26

1.17. Internal Embedded Memory.................................................................................26

1.18. Variable Precision DSP Block................................................................................ 27

1.19. Hard Processor System (HPS).............................................................................. 30

1.19.1. Key Features of the Intel Stratix 10 HPS....................................................31

1.20. Power Management............................................................................................ 34

1.21. Device Configuration and Secure Device Manager (SDM)......................................... 34

1.22. Device Security..................................................................................................36

1.23. Configuration via Protocol Using PCI Express..........................................................37

1.24. Partial and Dynamic Reconfiguration..................................................................... 37

1.25. Fast Forward Compile......................................................................................... 37

1.26. Single Event Upset (SEU) Error Detection and Correction.........................................38

1.27. Document Revision History for the Intel Stratix 10 TX Device Overview..................... 38

Contents

Intel® Stratix® 10 TX Device Overview

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