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MIMXRT8024DAF4A Datasheet(PDF) 39 Page - NXP Semiconductors |
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MIMXRT8024DAF4A Datasheet(HTML) 39 Page - NXP Semiconductors |
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39 / 103 page  RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or approximately 30 μs. NOTE WDOGn_B output signals (for each one of the Watchdog modules) do not have dedicated pins, but are muxed out through the IOMUX. See the IOMUX manual for detailed information. NOTE 4.4.3 SCAN JTAG Controller (SJC) timing parameters Figure 9 depicts the SJC test clock input timing. Figure 10 depicts the SJC boundary scan timing. Figure 11 depicts the SJC test access port. Signal parameters are listed in Table 30. JTAG_TCK (Input) VM VM VIH VIL SJ1 SJ2 SJ2 SJ3 SJ3 Figure 9. Test clock input timing diagram JTAG_TCK (Input) Data Inputs Data Outputs Data Outputs Data Outputs VIH VIL Input Data Valid Output Data Valid Output Data Valid SJ4 SJ5 SJ6 SJ7 SJ6 Figure 10. Boundary Scan (JTAG) timing diagram NXP Semiconductors Electrical Characteristics i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022 Data Sheet: Technical Data 39 / 103 |
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