MIMXRT8024DAF4A datasheet(76/103 Pages) NXP

76 / 103 page

ENET_CLK (input)

ENET_TX_EN

M16

M17

M18

M19

M20

M21

ENET_RX_DATA[1:0]

ENET_TX_DATA (output)

ENET_RX_ER

ENET_RX_EN (input)

Figure 51. RMII mode signal timing diagram

Table 68. RMII signal timing

Characteristic

Min.

Max.

Unit

M16

ENET_CLK pulse width high

35%

65%

ENET_CLK period

M17

ENET_CLK pulse width low

35%

65%

ENET_CLK period

M18

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid

—

M19

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid

—

M20

ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to

ENET_CLK setup

—

M21

ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER hold

—

4.9.5 Flexible Controller Area Network (FLEXCAN) AC electrical specifications

Please refer to General purpose I/O AC parameters.

4.9.6 LPUART electrical specifications

Please refer to General purpose I/O AC parameters.

4.9.7 USB PHY parameters

This section describes the USB-OTG PHY parameters.

The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision 2.0 OTG with the

following amendments.

• USB ENGINEERING CHANGE NOTICE

— Title: 5V Short Circuit Withstand Requirement Change

— Applies to: Universal Serial Bus Specification, Revision 2.0

• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000

• USB ENGINEERING CHANGE NOTICE

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

76 / 103

MIMXRT8024DAF4A Datasheet(PDF) 76 Page - NXP Semiconductors

MIMXRT8024DAF4A Datasheet(HTML) 76 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL