MIMXRT8024DAF4A datasheet(53/103 Pages) NXP

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Table 48. CSI ungated clock mode timing parameters

Parameter

Symbol

Min.

Max.

Units

CSI_VSYNC to pixel clock time

tVSYNC

33.5

—

CSI DATA setup time

tDsu

—

CSI DATA hold time

tDh

—

CSI pixel clock high time

tCLKh

3.75

—

CSI pixel clock low time

tCLKl

3.75

—

CSI pixel clock frequency

fCLK

—

MHz

The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as dumb or smart as follows:

• Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync (HSYNC)) and output-only

Bayer and statistics data.

• Smart sensors support CCIR656 video decoder formats and perform additional processing of the image (for example, image

compression, image pre-filtering, and various data output formats).

4.6.2 LCD Controller (LCDIF) timing parameters

Figure 30 shows the LCDIF timing and Table 49 lists the timing parameters.

LCDn_CLK

(falling edge capture)

LCDn_CLK

(rising edge capture)

LCDn_DATA[23:00]

LCDn Control Signals

Figure 30. LCD timing

Table 49. LCD timing parameters

Parameter

Symbol

Min

Max

Unit

LCD pixel clock frequency

tCLK(LCD)

—

MHz

LCD pixel clock high (falling edge capture)

tCLKH(LCD)

—

LCD pixel clock low (rising edge capture)

tCLKL(LCD)

—

LCD pixel clock high to data valid (falling edge capture)

td(CLKH-DV)

-1

Table continues on the next page...

NXP Semiconductors

Electrical Characteristics

i.MX RT1060X Crossover Processors for Extended Products , Rev. 1, 06/2022

Data Sheet: Technical Data

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