DFE252012P-2R2M datasheet(19/44 Pages) MICROCHIP

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DS20006388A-page 19

MCP16501

4.3.5

SELV2 AND SELV3 PINS

Pins SELV2 and SELV3 are meant to program the

default settings of some rails that must be activated

during the power-up sequence, but whose voltage val-

ues are application-dependent. These are Buck2 and

Buck3, the first being dedicated to DDRx/LPDDRx

power, while the latter being dedicated to core power.

The default values are selectable among three options,

corresponding to three different states of the relevant

pin: connected to ground (Low), connected to input

supply (High) or left unconnected (High-Z).

The Buck2 default voltage can be selected by means of

the SELV2 pin as follows:

TABLE 4-3:

VOUT2 DEFAULT VOLTAGE

VS. SELV2 PIN

The Buck3 default voltage can be selected by means of

the SELV3 pin as follows:

TABLE 4-4:

VOUT3 DEFAULT VOLTAGE

VS. SELV3 PIN

The statuses of SELV2 and SELV3 are frozen in a snap-

shot as soon as the VIN voltage exceeds the turn-on

Undervoltage Lockout Threshold (UVLO), as specified in

the “Electrical Characteristics” table. Any changes of

the SELV2 and SELV3 pins will have no effect after the

snapshot, and VIN must fall under the turn-off (lower)

UVLO threshold to unfreeze the snapshot.

Both pins are intended to be connected to GND (0V),

to VIN or left floating in the application. When left float-

ing, internal circuitry is initially activated to bias SELV2

and SELV3 at start-up for proper three-state (floating

state) detection.

For “Electrical Characteristics” table specification

purposes, the High State Threshold Voltage (VIHT)

and Low State Threshold Voltage (VILT) of pins SELV2

and SELV3 are given. They have both a minimum and

a maximum value specification.

At the time the snapshot is taken, those Min. and Max.

values should be used and interpreted as follows:

•If VIHT(MAX) < V(SELVx) ≤ V(VIN)  SELVx is

considered HIGH

•If 0V ≤ V(SELVx) < VILT(MIN)  SELVx is

considered LOW

•If VILT(MAX) < V(SELVx) < VIHT(MIN)  SELVx is

considered floating

If VIHT(MIN) ≤ V(SELVx) ≤ VIHT(MAX) or VILT(MIN) ≤

V(SELVx) ≤ VILT(MAX), then the logic status of SELVx

may not be interpreted correctly. Therefore, if the end

user chooses a connection different than the recom-

mended connection to GND, VIN or no connection, then

any usage of the SELVx pins within those boundaries

should be avoided. This is also illustrated in Figure 4-3

shown below:

FIGURE 4-3:

SELVx High, Low and Float

States Threshold.

4.3.6

nRSTO (RESET OUTPUT) PIN

Pin nRSTO is an active-low, open-drain output pin that

keeps the MPU in a Reset state. The nRSTO pin is

released (i.e., goes High-Z) with a 16ms delay upon

successful completion of a start-up sequence. nRSTO

is immediately asserted low when either the VIN volt-

age falls below the UVLO threshold, or a Fault condi-

tion is detected at system level (such as a Thermal

Shutdown) or an overcurrent condition is detected on

the Buck channels. Please see Section 5.4 “Protec-

tions” for more details on the Faults that would cause

the nRSTO signal low assertion. nRSTO also goes low

when the Hibernate mode is entered.

4.4

Power-up/Power-Down/Hibernate

Sequences and Timings

4.4.1

TYPICAL POWER-UP SEQUENCE

AND TIMING

The typical scenario applies to MPU applications,

where:

• I/O voltage (VDDIO) and, if applicable, auxiliary

SELV2 Status

VOUT2 Voltage

DDR Type

Low

1.2V

LPDDR2,

LPDDR3

High-Z

1.35V

DDR3L

High

1.8V

DDR2

SELV3 Status

VOUT3 Voltage

eMPU Type

Low

SAM9-5

High-Z

1.15V

SAM9-6 and

SAMA7G

High

1.25V

SAMA5D2x

Note:

SELV2 and SELV3 are always hardwired in

the final application and they cannot be

changed on-the-fly during operation.

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