DFE252012P-2R2M datasheet(16/44 Pages) MICROCHIP

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MCP16501

DS20006388A-page 16

 2020 Microchip Technology Inc.

4.1

Buck Channels and Related

External Components

The MCP16501 Buck channels are based on Peak

Current mode control architecture and have internal

frequency compensation for the voltage regulation

loop. The slope compensation is optimized for induc-

tors in the 1.5 µH to 2.2 µH range. A minimum output

capacitor of 22 µF is required for stability. Output

capacitance can be increased if necessary; however,

the maximum output capacitance value should be lim-

ited to avoid engaging the Hiccup mode overcurrent

protection during the initial soft start ramp. Further

details are given in Section 5.5 “Maximum Simulta-

neous Capacitive and DC Loading in Soft Start”.

The recommended input decoupling capacitance on

each Buck channel is 4.7 µF.

The Buck channels can operate in either Forced PWM

mode (Continuous Inductor Current mode), where the

inductor current is allowed to go negative, or in Auto-

matic PFM mode, where the inductor current is

prevented from going negative through Zero-Current

Detection (ZCD) and diode emulation of the low-side

MOSFET.

The switching frequency in Forced PWM Mode is

nominally 2 MHz.

4.2

LDO Channel and Related

External Components

The MCP16501 LDO is designed for operation with

low-ESR ceramic output capacitors of 2.2 µF (minimum

value) for loads up to 150 mA, and of 4.7 µF (minimum

value) for loads up to 300 mA. The total output capaci-

tance should not exceed 20 µF. Recommended capac-

itor

part

numbers

are

given

Section 5.1

“Recommended External Components”.

4.3

Control Signals and Power States

4.3.1

INTERFACING SIGNALS

The MCP16501 is interfaced to the host MPU by means

of the following signals: nSTRTO (open-drain output),

nRSTO (open-drain output), PWRHLD (input) and LPM

(input).The ESD protection on each interfacing signal is

purposely designed to prevent any leakage from the

MPU I/Os, even in the case where the main input power

is removed from the MCP16501.

4.3.2

nSTRT, nSTRTO, PWRHLD

FUNCTIONALITY

The nSTRT (push button input) serves as an external

wake-up input to the PMIC+MPU system. nSTRT is

internally pulled up to VIN and monitored. When the

nSTRT is pulled/detected as low (e.g., by means of a

push button or any other pull-down device) for longer

than a minimum debouncing time, the MCP16501

initiates the turn-on sequence.

The nSTRTO signal is asserted low whenever the

nSTRT is detected to be low; otherwise, it is High-Z

(typically, nSTRTO has an external pull-up resistor).

The only exception to this input (nSTRT)/output

(nSTRTO) relationship is the so called Automatic

Wake-up Pulse (AWKP) that is described in

Section 4.4.6 “Restart Sequence After Fault and

Automatic

Wake-up

Pulse

(AWKP)

Genera-

tion-MCP16501D only”(applicable to MCP16501D

only).

After the start-up sequence has been initiated, the

MCP16501 expects the assertion of the PWRHLD

signal (Power-Hold) from the MPU to validate the

start-up. PWRHLD could already be high in a typical

application using a backup supply. If PWRHLD has not

been asserted high by the MPU before the completion

of the start-up sequence (i.e., when nRSTO is about to

be asserted high), the MCP16501 will automatically

initiate a turn-off sequence.

During run time (PWRHLD = high), the nSTRT (thus

nSTRTO) can again be asserted low. No automatic

action is taken by the MCP16501 in this case.

4.3.3

nSTRT/PWRHLD TYPICAL USE

CASES

Depending on the presence of a backup supply and the

availability of an external wake-up signal connected at

nSTRT (“Button”), four different scenarios can be

defined for the turn-on of the MCP16501, as described

in Figure 4-1.

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