DFE252012P-2R2M datasheet(25/44 Pages) MICROCHIP

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DS20006388A-page 25

MCP16501

FIGURE 4-8:

Entering Hibernate Mode

Timing Diagram.

From the Hibernate state, the system can:

Move to OFF state (if LPM also goes low, the

VOUT2 can be immediately turned off); or

Initiate another start-up sequence (with the

exception of Buck2 which is already active) by a

low-to-high transition of PWRHLD.

The timing diagram of a start-up sequence from Hibernate

mode is shown in Figure 4-9. After the assertion of

PWRHLD, the MPU may deassert LPM at any time. Due

to internal filtering, simultaneous transition of LPM and

PWRHLD is allowed (hold time t5 can be 0 µs).

Depending on the time at which LPM is deasserted, the

MCP16501 may transition through the Low-Power

state or not.

FIGURE 4-9:

Start-up Sequence Exiting

Hibernate Mode Timing Diagram.

4.4.6

RESTART SEQUENCE AFTER

FAULT AND AUTOMATIC WAKE-UP

PULSE (AWKP)

GENERATION-MCP16501D ONLY

Due to the support for LPDDRx, which require correct

sequencing between the LPDDRx memory rails, the

MCP16501D features a different fault management

sequence. This consists in the turn-off of all channels

followed by an automatically executed restart

sequence, which ensures that the power rails will be

restarted in the correct order.

Please see Section 5.4 “Protections” for information

on which Faults may trigger a new restart sequence. In

the default configuration of the MCP16501D as soon as

a Fault is detected, the power delivery on all channels

Where:

t5 = Setup time, LPM = 1 to PWRHLD = 0:

Min. 0 µs (internal filtering applies)

t6 = Delay from PWRHLD deasserted to

nRSTO asserted: Min. 0 µs,

max. 10 µs (not a strict requirement)

t7 = Delay from nRSTO asserted to first

VOUTX turn-off: Min. 0 µs, max. 10 µs

(not a strict requirement)

Note:

Upon exit of Hibernate mode, Buck2 is not

part of the sequence because it is already

on (being in Auto-PFM mode). However,

also depending on the instant at which the

MPU deasserts LPM, it can toggle to

FPWM mode at the time nRSTO is deas-

serted.

Where:

t1 = Delay from PWRHLD asserted to first

supply VOUT1 starting (default 0.5 ms)

t3 =Time from VOUT1 established to VOUT3

starting (default 4 ms)

t4 =Time from VOUT3, established to

nRSTO deassertion (default 16 ms)

t5 = Minimum hold time, PWRHLD = 1 to

LPM = 0: Min. 0 µs (internal filtering

applies)

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