DFE252012P-2R2M datasheet(24/44 Pages) MICROCHIP

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MCP16501

DS20006388A-page 24

 2020 Microchip Technology Inc.

4.4.3

DROPOUT SAFE START-UP

SEQUENCE FEATURE

The start-up sequence management of MCP16501

ensures predictable timing between subsequent steps,

even if some power channels may operate in dropout

conditions with moderate loading.

This situation might occur for Buck1 because its output

voltage range (up to 3.7V) is overlapping the input sup-

ply range (2.7V-5.5V).

This operating condition is frequently encountered in

battery-powered applications. For example, some

loads designed for a 3.3V nominal supply voltage may

not be able to withstand the fully replenished battery

voltage (around 4.2V), and therefore, they would

require a front-end regulator. However, they could still

operate when the battery voltage has decreased low

enough to push their front-end regulator into dropout.

For example, if the battery voltage is around 3.1V and the

Buck1 output voltage is also set to 3.3V, it is still desirable

to start Buck1 and proceed throughout the start-up

sequence, even if the POK (Power OK) threshold for

Buck1 may not be reached, since Buck1 is still delivering

a voltage within the I/O operating voltage range. This

would allow a better exploitation of the battery because

the cutoff voltage is no longer dictated by the onset of the

dropout of the 3.3V regulator (Buck1) and by its POK

threshold.

By means of a dedicated circuit that monitors the

input-output differential during start-up of the potentially

affected regulators, the MCP16501 can still ensure a

proper start-up. The MPU can then detect the anomaly

(e.g. by measuring the output of Buck1) and decide

either to continue operation or to shut down the system.

The Start-up POK Bypass Threshold is the relevant

“Electrical Characteristics” table parameter that

defines the acceptable level of input-output differential,

to continue through the start-up sequence, in lack of

the normal POK.

4.4.4

TYPICAL POWER-DOWN

SEQUENCE AND TIMING

The power-down (shutdown) sequence can be initiated

by the MPU by deasserting PWRHLD (LPM being

already low or deasserted simultaneously). This

method assumes that the MCP16501 is in any

operating state (i.e., is outside the start-up sequence).

After PWRHLD has been deasserted nRSTO will

immediately be asserted low by the MCP16501. After

that, all active channels will be turned off, with the

exception of the LDO which is controlled by LEN. For

the MCP16501D, the LDO will be turned off by virtue of

the connection of LEN to VOUT1.

The turn-off of each channel also activates the active

discharge (if enabled) on the same channel.

The timing diagram in Figure 4-7 shows the typical

sequence for the power down

FIGURE 4-7:

Power-Down (Shutdown)

Sequence Timing Diagram.

4.4.5

TYPICAL HIBERNATE SEQUENCES

AND TIMING

The Hibernate mode entering sequence is similar to the

power-down, with the only difference is that LPM will be

asserted high by the MPU before deassertion of

PWRHLD, or at least at the same time PWRHLD is

deasserted (due to internal filtering, the setup time t5

can be as low as 0 µs). For example, taking the

MCP16501A variant into consideration, the VOUT2 rail

(and/or other rails which are defined as ON in

Hibernate mode by overwriting the default settings) will

remain active, while VOUT1 and VOUT3, will be immedi-

ately disabled. In Hibernate mode, the DDRx/LPDDRx

will typically be in Backup Self-Refresh mode (BSR).

The following timing diagram in Figure 4-8 shows the

typical Hibernate mode sequence for a device variant

that keeps only VOUT2 on in Hibernate mode (such as

MCP16501A).

Where:

t5 = Setup time, LPM = 0 to PWRHLD = 0:

Min. 0 µs (internal filtering applies)

t6 = Delay from PWRHLD deasserted to

nRSTO asserted: Min. 0 µs, max. 10 µs

(not a strict requirement)

t7 = Delay from nRSTO asserted to first

VOUTx turn-off: Min. 0 µs, max. 10 µs (not

a strict requirement)

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